View M30802MC-XXXGP_2983462.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 1 ------table of contents------ description the m16c/80 (144-pin version) group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 144-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 16m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling office, communications, industrial equipment, and other high-speed processing applications. the m16c/80 (144-pin version) group includes a wide range of products with different internal memory types and sizes and various package types. features ? memory capacity .................................. rom (see rom expansion figure.) ram 10 to 24 kbytes ? shortest instruction execution time ...... 50ns (f(x in )=20mhz) ? supply voltage ..................................... 4.2 to 5.5v (f(x in )=20mhz) mask rom and flash memory version 2.7 to 5.5v (f(x in )=10mhz) mask rom and flash memory version ? low power consumption ...................... 45ma (M30802MC-XXXGP) ? interrupts .............................................. 29 internal and 8 external interrupt sources, 5 software interrupt sources; 7 levels (including key input interrupt) ? multifunction 16-bit timer ...................... 5 output timers + 6 input timers ? serial i/o .............................................. 5 channels for uart or clock synchronous ? dmac .................................................. 4 channels (trigger: 31 sources) ? dramc ................................................ used for edo, fp, cas before ras refresh, self-refresh ? a-d converter ....................................... 10 bits x 8 channels (expandable up to 10 channels) ? d-a converter ....................................... 8 bits x 2 channels ? crc calculation circuit ......................... 1 circuit ? x-y converter ....................................... 1 circuit ? watchdog timer .................................... 1 line ? programmable i/o ............................... 123 lines ? input port .............................................. _______ 1 line (p8 5 shared with nmi pin) ? memory expansion .............................. available (16m bytes) ? chip select output ................................ 4 lines ? clock generating circuit ....................... 2 built-in clock generation circuits (built-in feedback resistance, and external ceramic or quartz oscillator) applications audio, cameras, office equipment, communications equipment, portable equipment, etc. cpu .............................................................. 11 reset ............................................................. 16 processor mode ............................................ 24 clock generating circuit ............................... 40 protection ...................................................... 52 outline of interrupt ........................................ 53 watchdog timer ............................................ 75 dmac ........................................................... 77 timer ............................................................. 88 serial i/o ..................................................... 120 specifications written in this manual are believed to be ac- curate, but are not guaranteed to be entirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition. a-d converter ............................................. 162 d-a converter ............................................. 172 crc calculation circuit .............................. 174 x-y converter ............................................. 176 dram controller ......................................... 179 programmable i/o ports ............................. 186 usage precaution ....................................... 203 electric characteristics ................................ 210 flash memory version ................................. 257
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 2 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 p9 6 /anex 1 /t x d 4 /sda 4 /srxd 4 p9 5 /anex 0 /clk 4 p9 2 /tb 2in /t x d 3 /sda 3 /srxd 3 p9 1 /tb 1in /r x d 3 /scl 3 /stxd 3 p9 0 /tb 0in /clk3 p14 6 p14 5 p14 4 p14 3 p14 1 p14 2 p14 0 byte cnv ss p8 7 /x cin p8 6 /x cout x out v ss x in v cc p8 0 /ta 4out /u p7 7 /ta 3in p7 6 /ta 3out p7 4 /ta 2out /w p7 2 /clk 2 /ta 1out /v (note) p7 1 /r x d 2 /scl 2 /ta 0in /tb 5in (note) p9 4 /da 1 /tb 4in /cts 4 /rts 4 /ss 4 p9 3 /da 0 /tb 3in /cts 3 /rts 3 /ss 3 reset p8 5 /nmi p8 4 /int 2 p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p7 5 /ta 2in /w p7 3 /cts 2 /rts 2 /ta 1in /v 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 p7 0 /t x d 2 /sda 2 /ta 0out p6 7 /t x d 1 v cc p6 6 /r x d 1 v ss p6 5 /clk 1 p6 3 /t x d 0 p6 2 /r x d 0 p6 1 /clk 0 p13 7 p13 6 p13 5 p13 4 p13 3 v ss p13 2 v cc p13 1 p13 0 p5 3 /bclk/ale/clk out p12 7 p12 6 p12 5 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p6 0 /cts 0 /rts 0 p5 6 /ale/ras p5 5 /hold p5 4 /hlda/ale p5 2 /rd/dw p5 1 /wrh/bhe/cash p5 0 /wrl/wr/casl p4 7 /cs0/a 23 p4 6 /cs1/a 22 p4 5 /cs2/a 21 p4 4 /cs3/a 20 (ma12) p4 3 /a 19 (ma11) v cc p4 2 /a 18 (ma10) v ss p4 1 /a 17 (ma9) p4 0 /a 16 (ma8) p3 7 /a 15 (ma7)(/d 15 ) p3 6 /a 14 (ma6)(/d 14 ) p3 5 /a 13 (ma5)(/d 13 ) p3 4 /a 12 (ma4)(/d 12 ) p3 3 /a 11 (ma3)(/d 11 ) p3 2 /a 10 (ma2)(/d 10 ) p3 1 /a 9 (ma1)(/d 9 ) p12 4 p12 3 p12 2 p12 1 p12 0 v cc p3 0 /a 8 (ma0)(/d 8 ) p2 7 /a 7 (/d 7 ) p2 6 /a 6 (/d 6 ) p2 5 /a 5 (/d 5 ) p2 4 /a 4 (/d 4 ) p2 3 /a 3 (/d 3 ) p2 2 /a 2 (/d 2 ) p2 1 /a 1 (/d 1 ) p2 0 /a 0 (/d 0 ) v ss p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 5 /d 13 /int3 p1 6 /d 14 /int4 p1 7 /d 15 /int5 p1 0 /d 8 p0 7 /d 7 p0 6 /d 6 p0 5 /d 5 p0 4 /d 4 p11 4 p11 3 p11 2 p11 1 p11 0 p0 3 /d 3 p0 2 /d 2 p0 1 /d 1 p0 0 /d 0 p15 7 p15 6 p15 5 p15 4 p15 3 p15 2 p15 1 v ss p15 0 v cc p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref av cc p10 7 /an 7 /ki3 p10 6 /an 6 /ki2 p10 5 /an 5 /ki1 p10 4 /an 4 /ki0 p9 7 /ad trg /r x d 4 /scl 4 /stxd 4 73 74 75 76 77 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 78 p5 7 /rdy 12 3 4 7 6 8 9 101112 13141516 17181920 21222324252627282930 5 31 32 33 34 35 36 note: this port is n-channel open drain output. m30802-xxxgp pin configuration figure 1.1.1 show the pin configurations (top view). pin configuration (top view) package: 144p6q-a figure 1.1.1. pin configuration (top view)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 3 block diagram figure 1.1.2 is a block diagram of the m16c/80 (144-pin version) group. block diagram of the M30802MC-XXXGP figure 1.1.2. block diagram of M30802MC-XXXGP aaaaa aaaaa r0l r0h r1h r1l r2 aaaaaa a aaaa a a aaaa a a aaaa a aaaaaa i/o ports 8888888 8 7 8 8 internal peripheral functions timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) timer tb3 (16 bits) timer tb4 (16 bits) timer tb5 (16 bits) watchdog timer (15 bits) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels expandable up to 10 channels) uart /clock synchronous si/o (8 bits x 5 channels) x-y converter (16 bits x 16 bits) crc arithmetic circuit (ccitt) (polynomial : x +x +x +1) system clock generator x in - x out x cin - x cout memory dram controller m16c/80 series 16-bit cpu core registers r0h r0l r1h r1l r2 r3 a0 a1 fb sb dram controller multiplier port p0 port p1 port p2 port p3 port p4 port p5 port p6 port p7 port p8 port p8 5 port p9 port p10 flg intb isp usp pc svf svp vct 12 16 5 rom (note 1) ram (note 2) note 1: rom size depends on mcu type. note 2: ram size depends on mcu type. port p15 port p14 port p13 port p12 port p11 87885
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 4 item performance number of basic instructions 106 instructions shortest instruction execution time 50ns(f(x in )=20mhz) memory see rom expansion figure. capacity 10 to 24 k bytes i/o port 8 bits x 13, 7 bits x 2, 5 bits x 1 input port 1 bit x 1 multifunction 16 bits x 5 timer 16 bits x 6 serial i/o (uart or clock synchronous) x 5 a-d converter 10 bits x (8 + 2) channels d-a converter 8 bits x 2 dmac 4 channels dram controller cas before ras refresh, self-refresh, edo, fp crc calculation circuit crc-ccitt x-y converter 16 bits x 16 bits watchdog timer 15 bits x 1 (with prescaler) interrupt 29 internal and 8 external sources, 5 software sources, 7 levels clock generating circuit 2 built-in clock generation circuits (built-in feedback resistance, and external ceramic or quartz oscillator) supply voltage 4.2 to 5.5v (f(x in )=20mhz) mask rom and flash memory version 2.7 to 5.5v (f(x in )=10mhz) mask rom and flash memory version power consumption 45ma (f(x in ) = 20mhz without software wait,vcc=5v) mask rom 128 kbytes version i/o 5v characteristics 5ma memory expansion available (up to 16m bytes) operating ambient temperature C40 to 85 o c device configuration cmos high performance silicon gate package 144-pin plastic mold qfp table 1.1.1. performance outline of m16c/80 (144-pin version) group performance outline table 1.1.1 is a performance outline of m16c/80 (144-pin version) group. rom ram p0 to p15 (except p8 5 ) p8 5 ta0, ta1, ta2, ta3,ta4 tb0, tb1, tb2, tb3, tb4, tb5 uart0, uart1, uart2, uart3, uart4 i/o withstand voltage output current
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 5 mitsubishi plans to release the following products in the m16c/80 (144-pin version) group: (1) support for mask rom version, external rom version and flash memory version (2) rom capacity (3) package 144p6q : plastic molded qfp (mask rom version and flash memory version) the m16c/80 (144-pin version) group products currently supported are listed in table 1.1.2. ram capacity rom capacity package type remarks type no 10k bytes mask rom version as of june, 2000 M30802MC-XXXGP 128k bytes m30802fcgp ** ** :under development flash memory version 144p6q-a m30805fggp ** 20k bytes 256k bytes m30802sgp 10k bytes external rom version 20k bytes m30805mg-xxxgp 256k bytes 10k bytes 128k bytes m30805sgp 24k bytes table 1.1.2. m16c/80 (144-pin version) group figure 1.1.3. rom expansion rom size (byte) external rom 128k 96k 64k 32k mask rom version flash memory version external rom version 80k 256k M30802MC-XXXGP m30802fcgp m30805fggp m30802sgp m30805mg-xxxgp m30805sgp
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description 6 figure 1.1.4. type no., memory size, and package package type: gp : package 144p6q-a rom no. omitted for blank external rom version and flash memory version rom capacity: c : 128k bytes g : 256k bytes memory type: m : mask rom version s : external rom version f : flash memory version type no. m 3 0 8 0 2 m c ? x x x g p m16c/80 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning)
pin description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 7 v cc , v ss cnv ss x in x out byte av cc av ss v ref p0 0 to p0 7 d 0 to d 7 p1 0 to p1 7 d 8 to d 15 p2 0 to p2 7 a 0 to a 7 a 0 /d 0 to a 7 /d 7 p3 0 to p3 7 a 8 to a 15 a 8 /d 8 to a 15 /d 15 signal name power supply input cnv ss reset input clock input clock output external data bus width select input analog power supply input reference voltage input i/o port p0 i/o port p1 i/o port p2 i/o port p3 supply 4.2 to 5.5 v to the v cc pin. supply 0 v to the v ss pin. function this pin switches between processor modes. connect it to the v ss when operating in single-chip or memory expansion mode after reset. connect it to the v cc when in microprocessor mode after reset. a ?? on this input resets the microcomputer. these pins are provided for the main clock generating circuit. connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin selects the width of an external data bus. a 16-bit width is selected when this input is ?? an 8-bit width is selected when this input is ?? this input must be fixed to either ?? or ?? when not using the external bus,connect this pin to v ss . this pin is a power supply input for the a-d converter. connect this pin to v cc . this pin is a power supply input for the a-d converter. connect this pin to v ss . this pin is a reference voltage input for the a-d converter. this is an 8-bit cmos i/o port. it has an input/output port direction register that allows the user to set each pin for input or output individually. when set for input in single chip mode, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. in memory expansion and microprocessor mode, an built-in pull-up resistance cannot be used. however, it is possible to select pull-up resistance presence to the usable port as i/o port by setting. when set as a separate bus, these pins input and output data (d 0 ? 7 ). this is an 8-bit i/o port equivalent to p0. p1 5 to p1 7 also function as external interrupt pins as selected by software. when set as a separate bus, these pins input and output data (d 8 ? 15 ). this is an 8-bit i/o port equivalent to p0. these pins output 8 low-order address bits (a 0 ? 7 ). if a multiplexed bus is set, these pins input and output data (d 0 ? 7 ) and output 8 low-order address bits (a 0 ? 7 ) separated in time by multiplexing. this is an 8-bit i/o port equivalent to p0. these pins output 8 middle-order address bits (a 8 ? 15 ). if the external bus is set as a 16-bit wide multiplexed bus, these pins input and output data (d 8 ? 15 ) and output 8 middle-order address bits (a 8 ? 15 ) separated in time by multiplexing. pin name input input input output input input input/output input/output input/output input/output i/o type analog power supply input input/output output input/output input/output output input/output reset ma0 to ma7 if accessing to dram area, these pins output row address and column address separated in time by multiplexing. output pin description
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer pin description 8 pin description signal name function pin name i/o type i/o port p5 input/output input/output input/output input/output input/output input/output input input/output input/output i/o port p6 i/o port p7 i/o port p8 i/o port p8 5 i/o port p9 i/o port p10 p5 0 to p5 7 p6 0 to p6 7 p7 0 to p7 7 p8 0 to p8 4 , p8 6 , p8 7 , p8 5 p9 0 to p9 7 p10 0 to p10 7 this is an 8-bit i/o port equivalent to p0. p5 3 in this port outputs a divide-by-8 or divide-by-32 clock of x in or a clock of the same frequency as x cin as selected by software. output output output output output input output input this is an 8-bit i/o port equivalent to p0. when set for input in single chip mode, the user can specify in units of four bits via software whether or not they are tied to a pull-up resistance. in memory expansion and microprocessor mode, an built-in pull-up resistance cannot be used. pins in this port also function as uart0 and uart1 i/ o pins as selected by software. this is an 8-bit i/o port equivalent to p6 (p7 0 and p7 1 are n-channel open drain output). pins in this port also function as timer a 0 Ca 3 , timer b5 or uart2 i/o pins as selected by software. this is an 8-bit i/o port equivalent to p6. pins in this port also function as uart3 and uart4 i/o pins, timer b0Cb4 input pins, d-a converter output pins, a-d converter extended input pins, or a-d trigger input pins as selected by software. this is an 8-bit i/o port equivalent to p6. pins in this port also function as a-d converter input pins. furthermore, p10 4 Cp10 7 also function as input pins for the key input interrupt function. wrl / wr, wrh / bhe, rd, bclk, hlda, hold, ale, rdy output wrl, wrh (wr and bhe), rd, bclk, hlda, and ale signals. wrl and wrh, and bhe and wr can be switched using software control. wrl, wrh, and rd selected with a 16-bit external data bus, data is written to even addresses when the wrl signal is l and to the odd addresses when the wrh signal is l. data is read when rd is l. wr, bhe, and rd selected data is written when wr is l. data is read when rd is l. odd addresses are accessed when bhe is l. use this mode when using an 8-bit external data bus. while the input level at the hold pin is l, the microcomputer is placed in the hold state. while in the hold state, hlda outputs a l level. ale is used to latch the address. while the input level of the rdy pin is l, the microcomputer is in the ready state. p8 0 to p8 4 , p8 6 , and p8 7 are i/o ports with the same functions as p6. using software, they can be made to function as the i/o pins for timer a4 and the input pins for external interrupts. p8 6 and p8 7 can be set using software to function as the i/o pins for a sub clock generation circuit. in this case, connect a quartz oscillator between p8 6 (x cout pin) and p8 7 (x cin pin). p8 5 is an input-only port that also functions for nmi. the nmi interrupt is generated when the input at this pin changes from h to l. the nmi function cannot be canceled using software. the pull-up cannot be set for this pin. dw, casl, cash, ras output output output output when accessing to dram area while dw signal is l, write to dram. casl and cash show timing when latching to line address. when casl accesses to even address, and cash to odd, these two pins become l. ras signal shows timing when latching to row address. p4 0 to p4 7 i/o port p4 this is an 8-bit i/o port equivalent to p0. input/output output output cs 0 to cs 3 these pins output cs 0 Ccs 3 signals. cs 0 Ccs 3 are chip select signals used to specify an access space. a 16 to a 22 , a 23 output these pins output 8 high-order address bits (a 16 Ca 22 , a 23 ). highest address bit (a 23 ) outputs inversely. ma8 to ma12 if accessing to dram area, these pins output data separated in time by multiplexing.
pin description under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 9 signal name function pin name i/o type input/output i/o port p11 p11 0 to p11 4 this is an 5-bit i/o port equivalent to p6. input/output i/o port p12 p12 0 to p12 7 this is an 8-bit i/o port equivalent to p6. input/output i/o port p13 p13 0 to p13 7 this is an 8-bit i/o port equivalent to p6. input/output i/o port p14 p14 0 to p14 6 this is an 7-bit i/o port equivalent to p6. input/output i/o port p15 p15 0 to p15 7 this is an 8-bit i/o port equivalent to p6. pin description
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer memory 10 operation of functional blocks the m16c/80 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, dram controller and i/o ports. the following explains each unit. memory figure 1.2.1 is a memory map of the m16c/80 group. the address space extends the 16 mbytes from address 000000 16 to ffffff 16 . from ffffff 16 down is rom. for example, in the M30802MC-XXXGP, there is 128k bytes of internal rom from fe0000 16 to ffffff 16 . the vector table for fixed interrupts such _______ as the reset and nmi are mapped to ffffdc 16 to ffffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 000400 16 up is ram. for example, in the M30802MC-XXXGP, 10 kbytes of internal ram is mapped to the space from 000400 16 to 002bff 16 . in addition to storing data, the ram also stores the stack used when calling subroutines and when interrupts are generated. the sfr area is mapped to 000000 16 to 0003ff 16 . this area accommodates the control registers for peripheral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. figure 1.5.1 to 1.5.4 are location of peripheral unit control registers. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to fffe00 16 to ffffdb 16 . if the starting addresses of subrou- tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc- tions can be used as 2-byte instructions, reducing the number of program steps. in memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be used. for example, in the M30802MC-XXXGP, the following spaces cannot be used. ? the space between 002c00 16 and 008000 16 (memory expansion and microprocessor modes) ? the space between f00000 16 and fdffff 16 (memory expansion mode) figure 1.2.1. memory map 000000 16 yyyyyy 16 ffffff 16 000400 16 008000 16 xxxxxx 16 f00000 16 aaaaa a aaa a a aaa a aaaaa external area internal rom area sfr area for details, see figures 1.5.1 to 1.5.4 internal ram area internal reserved area (note 1) internal reserved area (note 2) fffe00 16 ffffdc 16 ffffff 16 note 1: during memory expansion and microprocessor modes, can not be used. note 2: in memory expansion mode, can not be used. undefined instruction overflow brk instruction address match watchdog timer reset special page vector table nmi address xxxxx 16 fe0000 16 002bff 16 m30802mc/fc type no. address yyyyy 16 fc0000 16 0053ff 16 m30805mg/fg 002bff 16 m30802s 0063ff 16 m30805s
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu 11 central processing unit (cpu) the cpu has a total of 28 registers shown in figure 1.3.1. seven of these registers (r0, r1, r2, r3, a0, a1, sb and fb) come in two sets; therefore, these have two register banks. figure 1.3.1. central processing unit register b23 b7 b0 flag register address register (note) static base register (note) frame base register (note) user stack pointer interrupt stack pointer interrupt table register flag save register pc save register vector register dma mode register dma transfer count register dma transfer count reload register dma memory address register dma sfr address register dma memory address reload register b15 b0 b15 b0 b23 b15 b23 data register (note) flg r0h r1h r2 r3 a0 a1 sb fb usp isp intb pc svf vct dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dsa0 dsa1 dra0 dra1 svp dmac related register program counter r2 r3 high-speed interrupt register general register b31 r0l r1l note: these registers have two register banks.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu 12 (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, r3, r2r0 and r3r1) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h/r1h), and low-order bits as (r0l/r1l). registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0/r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 24 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. (3) static base register (sb) static base register (sb) is configured with 24 bits, and is used for sb relative addressing. (4) frame base register (fb) frame base register (fb) is configured with 24 bits, and is used for fb relative addressing. (5) program counter (pc) program counter (pc) is configured with 24 bits, indicating the address of an instruction to be executed. (6) interrupt table register (intb) interrupt table register (intb) is configured with 24 bits, indicating the start address of an interrupt vector table. (7) user stack pointer (usp), interrupt stack pointer (isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 24 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). set usp and isp to an even number so that execution efficiency is increased. (8) save flag register (svf) this register consists of 16 bits and is used to save the flag register when a high-speed interrupt is generated.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu 13 (9) save pc register (svp) this register consists of 24 bits and is used to save the program counter when a high-speed interrupt is generated. (10) vector register (vct) this register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is generated. (11) dma mode registers (dmd0/dmd1) these registers consist of 8 bits and are used to set the transfer mode, etc. for dma. (12) dma transfer count registers (dct0/dct1) these registers consist of 16 bits and are used to set the number of dma transfers performed. (13) dma transfer count reload registers (drc0/drc1) these registers consist of 16 bits and are used to reload the dma transfer count registers. (14) dma memory address registers (dma0/dma1) these registers consist of 24 bits and are used to set a memory address at the source or destination of dma transfer. (15) dma sfr address registers (dsa0/dsa1) these registers consist of 24 bits and are used to set a fixed address at the source or destination of dma transfer. (16) dma memory address reload registers (dra0/dra1) these registers consist of 24 bits and are used to reload the dma memory address registers.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu 14 (17) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure 1.3.2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu 15 figure 1.3.2. flag register (flg) carry flag debug flag zero flag sign flag register bank select flag overflow flag interrupt enable flag stack pointer select flag reserved area processor interrupt priority level reserved area flag register (flg) aa aa aa aa a a aa aa aaaaaaa aaaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl b0 b15 ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer reset 16 figure 1.4.2. reset sequence reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure 1.4.1 shows the example reset circuit. figure 1.4.2 shows the reset sequence. figure 1.4.1. example reset circuit bclk address address address microprocessor mode byte = ? microprocessor mode byte = ? content of reset vector single chip mode bclk 24cycles ffffc 16 ffffd 16 ffffe 16 content of reset vector ffffc 16 ffffe 16 content of reset vector ffffe 16 x in reset rd wr cs0 rd wr cs0 ffffc 16 more than 20 cycles are needed reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.2v example when f(x in ) = 10mhz and v cc = 5v .
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer reset 17 ____________ table 1.4.1 shows the statuses of the other pins while the reset pin level is l. figures 1.4.3 and 1.4.4 show the internal status of the microcomputer immediately after the reset is cancelled. ____________ table 1.4.1. pin status when reset pin level is l status cnv ss = v cc cnv ss = v ss byte = v ss byte = v cc pin name p0 p1 p2, p3, p4 p5 0 p5 1 p5 2 p5 3 p5 4 p5 5 p5 6 p5 7 p6, p7, p8 0 to p8 4 , p8 6 , p8 7 , p9, p10, p11, p12, p13, p14, p15 input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) input port (floating) data input (floating) data input (floating) address output (undefined) bclk output ras output wr output (??level is output) rd output (??level is output) rdy input (floating) input port (floating) bclk output bhe output (undefined) hlda output (the output value depends on the input to the hold pin) hold input (floating) data input (floating) address output (undefined) input port (floating) input port (floating) rdy input (floating) ras output hold input (floating) hlda output (the output value depends on the input to the hold pin) rd output (??level is output) bhe output (undefined) wr output (??level is output)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer reset 18 figure 1.4.3. device's internal status after a reset is cleared x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. note: when the v cc level is applied to the cnv ss pin, it is 03 16 at a reset. (1) (0004 16 ) processor mode register 0 (note) 80 16 (2) (0005 16 ) processor mode register 1 (3) (0006 16 ) system clock control register 0 (4) (0007 16 ) system clock control register 1 (5) (0008 16 ) wait control register (6) (0009 16 ) address match interrupt enable register 0 0 (7) protect register (000a 16 ) 00 0 (10) (000f 16 ) watchdog timer control register 0 0? 0???? (12) (0014 16 ) address match interrupt register 1 (0018 16 ) 00 16 00 16 (0040 16 ) dmam control register ?? ??? dma0 interrupt control register (21) (006b 16 ) uart0 receive interrupt control register ? 0 0 0 (22) (006c 16 ) ? 0 0 0 (23) (006d 16 ) key input interrupt control register ? 0 0 0 (20) (006a 16 ) bus collision detection(uart3) interrupt control register 0 0 0 ? (8) external data bus width control register (000b 16 ) (0010 16 ) address match interrupt register 0 (0011 16 ) (0012 16 ) 00 16 00 16 (11) timer b2 interrupt control register (15) dma2 interrupt control register ?000 (16) uart2 receive/ack interrupt control register ?000 (17) timer a0 interrupt control register ?000 (18) (0068 16 ) uart3 receive/ack interrupt control register (19) (0069 16 ) (24) a-d conversion interrupt control register (25) (26) (0073 16 ) ? 0 0 0 (0074 16 ) (0076 16 ) ? 0 0 0 ? 0 0 0 00 16 (27) (28) (29) (30) uart1 transmit interrupt control register (31) (32) (33) (34) (35) (36) (37) timer b0 interrupt control register timer b2 interrupt control register (38) timer b3 interrupt control register (39) int5 interrupt control register (40) int3 interrupt control register (41) int1 interrupt control register (45) three-phase output buffer register 0 (46) three-phase output buffer register 1 three-phase pwm control register 0 (43) three-phase pwm control register 1 (44) (42) timer b3,4,5 count start flag (47) timer b3 mode register (48) timer b4 mode register (49) timer b5 mode register (50) uart4 transmit/receive control register 1 uart4 transmit/receive control register 0 (56) uart4 transmit/receive mode register (54) (55) (52) (53) uart4 special mode register 2 (51) 0 0 (9) (000c 16 ) main clock divided register 08 16 (13) address match interrupt register 2 (14) address match interrupt register 3 (0015 16 ) 00 16 (0016 16 ) 00 16 (0019 16 ) 00 16 (001a 16 ) 00 16 (001c 16 ) 00 16 (001d 16 ) 00 16 (001e 16 ) 00 16 timer a2 interrupt control register uart4 receive/ack interrupt control register timer a4 interrupt control register uart1 receive interrupt control register timer b1 interrupt control register bus collision detection(uart2) interrupt control register dma1 interrupt control register uart2 transmit/nack interrupt control register uart3 transmit/nack interrupt control register timer a1 interrupt control register uart4 receive/nack interrupt control register timer a3 interrupt control register dma3 interrupt control register bus collision detection(uart4) interrupt control register uart0 transmit interrupt control register int4 interrupt control register int2 interrupt control register int0 interrupt control register exit priority register xy control register uart4 special mode register timer b4 interrupt control register (006e 16 ) (006f 16 ) (0070 16 ) (0071 16 ) (0072 16 ) 00 0 20 16 ff 16 00 0 01 00 16 ?000 ?000 ?000 ?000 (0078 16 ) (007a 16 ) (007c 16 ) (007e 16 ) ? 0 0 0 ? 000 ? 000 ? 000 (0088 16 ) (0089 16 ) (008a 16 ) (008b 16 ) (008e 16 ) (008f 16 ) (0090 16 ) (0091 16 ) (0092 16 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 (008c 16 ) ? 0 0 0 (008d 16 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 ? 000 ? 000 00? 0000 00? 0000 (0309 16 ) (030a 16 ) 00 16 (030b 16 ) 00 16 (0308 16 ) 00 16 (0300 16 ) (031b 16 ) (031c 16 ) 00? 0000 (031d 16 ) 00 00 00 (0093 16 ) (0094 16 ) (0096 16 ) (009c 16 ) (009e 16 ) (009f 16 ) (02e0 16 ) (02f6 16 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 (0098 16 ) ? 0 0 0 (009a 16 ) ? 000 ? 000 ? 000 0 000 00 00 00 00 00 16 (02f7 16 ) 00 16 (02f8 16 ) 00 16 (02fc 16 ) 08 16 (02fd 16 ) 02 16 ? (62) (63) (60) (59) (61) (64) (65) (66) (57) (58) uart4 special mode register 3 (02f5 16 ) 00 16 (67) 000 ?000 0 000
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer reset 19 figure 1.4.4. device's internal status after a reset is cleared trigger select flag up-down flag timer a0 mode register timer a1 mode register timer a2 mode register timer b0 mode register timer b1 mode register timer b2 mode register timer a3 mode register timer a4 mode register one-shot start flag uart1 transmit/receive control register 0 uart1 transmit/receive control register 1 uart transmit/receive control register 2 dma0 cause select register dma1 cause select register uart0 transmit/receive mode register uart0 transmit/receive control register 0 uart0 transmit/receive control register 1 uart1 transmit/receive mode register a-d control register 2 a-d control register 0 a-d control register 1 count start flag clock prescaler reset flag x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. port p0 direction register port p1 direction register port p2 direction register port p3 direction register port p4 direction register port p5 direction register port p6 direction register port p7 direction register port p8 direction register port p9 direction register port p10 direction register pull-up control register 0 pull-up control register 1 pull-up control register 2 port control register frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) data registers (r0/r1/r2/r3) (78) (77) (79) (80) (83) (84) (85) (86) (82) (76) (81) (90) (91) (92) (93) (94) (95) (87) (88) (89) (96) (74) (73) (71) (72) (68) (69) (70) (75) (97) (99) (98) (103) (104) (105) (102) (101) (100) (114) (115) (116) (117) (118) (119) (120) (121) (122) (123) (124) (125) (126) (127) (132) (130) (131) (128) (129) (132) (136) (137) (138) (133) (135) (142) (143) (139) (141) (140) (109) (110) (111) (112) (113) (106) (107) (033d 16 ) (0340 16 ) (0341 16 ) (0342 16 ) (0357 16 ) (0358 16 ) (0359 16 ) (0344 16 ) (0356 16 ) (033c 16 ) 02 16 00 16 00 16 (0343 16 ) 00 16 00 16 (035d 16 ) (0360 16 ) (0364 16 ) (0365 16 ) (0368 16 ) (036c 16 ) (035a 16 ) (035b 16 ) 00? 0000 ? (035c 16 ) 00? 0000 00 16 08 16 02 16 (036d 16 ) 0 01 0000 (0337 16 ) 00 16 (032c 16 ) (0336 16 ) (032d 16 ) (0325 16 ) (0327 16 ) (0328 16 ) 08 16 00 16 00 16 00 16 (031f 16 ) 000 000 02 16 00 16 (0338 16 ) 00 16 0 000 0?00 0 000 0?00 0 000 0?00 0 000 0?00 0 000 0?00 0 00? 0000 00 16 08 16 02 16 (0370 16 ) 00 0000 0 000 000 0 000 000 (0379 16 ) (0378 16 ) 0 0 000 0 (0396 16 ) (0397 16 ) 00 16 (108) d-a control register (039c 16 ) 00 16 0 000 0 (0394 16 ) ??? 000 000 0 000 000 (037b 16 ) (037a 16 ) 0 00 16 0 0 000 (03c2 16 ) (03c3 16 ) (03c6 16 ) (03c7 16 ) (03ca 16 ) (03da 16 ) (03db 16 ) (03e2 16 ) (03e3 16 ) (03e6 16 ) (03e7 16 ) (03ea 16 ) (03eb 16 ) (03f0 16 ) 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 00 16 0000 16 000000 16 000000 16 (03f1 16 ) x0 16 0 (03ff 16 ) 000000 16 000000 16 000000 16 0000 16 00 16 000000 16 ?? ?? ?? ?? ?? 0 0 00 000 0 0 000 0 0 0 (03af 16 ) (03b0 16 ) (03b2 16 ) (03b3 16 ) (03b4 16 ) (03b5 16 ) (03b6 16 ) 00 16 0 0 00 000 (03b1 16 ) 0 00 0 0 0 0 interrupt cause select register uart3 transmit/receive control register 1 uart3 transmit/receive control register 0 uart3 transmit/receive mode register uart3 special mode register 3 uart3 special mode register uart2 transmit/receive control register 1 uart2 transmit/receive control register 0 uart2 transmit/receive mode register uart2 special mode register 2 uart2 special mode register dma2 cause select register dma3 cause select register pull-up control register 3 dma mode register (dmd0/dmd1) dma transfer count register (dct0/dct1) dma transfer count reload register (drc0/drc1) dma memory address register (dma0/dma1) dma sfr address register (dsa0/dsa1) dma memory address reload register (dra0/dra1) function select register c function select register a0 function select register b0 function select register a1 function select register a2 function select register a3 function select register b1 function select register b2 (0326 16 ) 00 16 uart3 special mode register 2 (0335 16 ) uart2 special mode register 3 (03b7 16 ) function select register b3 0 00 ? 00 0?? 0 ? (146) (147) (145) (144) port p11 direction register (03cb 16 ) port p12 direction register (03ce 16 ) 00 16 port p13 direction register (03cf 16 ) 00 16 port p14 direction register (03d2 16 ) port p15 direction register (03d3 16 ) 00 16 0 0 000 0 0 0 0 000 0 0 (03dc 16 ) 00 16 pull-up control register 4 (148) (152) (153) (149) (151) (150) (0377 16 ) flash memory control register 0 (note) ? 00001 0 (102) (101) 0?? ??? (0376 16 ) flash memory control register 1 (note) ? note :this register exists in the flash memory version.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer sfr 20 figure 1.5.1. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0060 16 0061 16 0062 16 0063 16 0064 16 0065 16 0066 16 0067 16 0068 16 0069 16 006a 16 006b 16 006c 16 006d 16 006e 16 006f 16 0070 16 0071 16 0072 16 0073 16 0074 16 0075 16 0076 16 0077 16 0078 16 0079 16 007a 16 007b 16 007c 16 007d 16 007e 16 007f 16 0080 16 0081 16 0082 16 0083 16 0084 16 0085 16 0086 16 0087 16 0088 16 0089 16 008a 16 008b 16 008c 16 008d 16 008e 16 008f 16 0090 16 0091 16 0092 16 0093 16 0094 16 0095 16 0096 16 0097 16 0098 16 0099 16 009a 16 009b 16 009c 16 009d 16 009e 16 009f 16 00a0 16 00a1 16 00a2 16 00a3 16 00a4 16 watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) wait control register (wcr) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) external data bus widthcontrol register (ds) main clock division register (mcd) address match interrupt register 2 (rmad2) address match interrupt register 3 (rmad3) emulator interrupt vector table register (eiad) emulator interrupt detect register (eitd) emulator protect register (eprr) rom areaset register (roa) debug monitor area set register (dba) expansion area set register 0 (exa0) expansion area set register 1 (exa1) expansion area set register 2 (exa2) expansion area set register 3 (exa3) dram control register (dramcont) dram reflesh interval set register (refcnt) timer a1 interrupt control register (ta1ic) uart0 transmit interrupt control register (s0tic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) uart0 receive interrupt control register (s0ric) uart2 transmit/nack interrupt control register (s2tic) uart1 receive interrupt control register (s1ric) dma2 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) key input interrupt control register (kupic) a-d conversion interrupt control register (adic) bus collision detection(uart3) interrupt control register (bcn3ic) uart2 receive/ack interrupt control register (s2ric) int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a3 interrupt control register (ta3ic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a4 interrupt control register (ta4ic) int3 interrupt control register (int3ic) timer b5 interrupt control register (tb5ic) timer b4 interrupt control register (tb4ic) timer b3 interrupt control register (tb3ic) int5 interrupt control register (int5ic) int4 interrupt control register (int4ic) uart3 receive/ack interrupt control register (s3ric) uart4 receive/ack interrupt control register (s4ric) uart3 transmit/nack interrupt control register (s3tic) uart4 transmit/nack interrupt control register (s4tic) exit priority register (rlvl) uart1 transmit interrupt control register (s1tic) dma1 interrupt control register (dm1ic) dma3 interrupt control register (dm3ic) bus collision detection(uart2) interrupt control register (bcn2ic) bus collision detection(uart4) interrupt control register (bcn4ic) * * * * * * * * * * as this register is used exclusively for debugger purposes, user cannot use this. do not access to the register. (the blank area is reserved and cannot be used by user.)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer sfr 21 figure 1.5.2. location of peripheral unit control registers (2) 0300 16 0301 16 0302 16 0303 16 0304 16 0305 16 0306 16 0307 16 0308 16 0309 16 030a 16 030b 16 030c 16 030d 16 030e 16 030f 16 0310 16 0311 16 0312 16 0313 16 0314 16 0315 16 0316 16 0317 16 0318 16 0319 16 031a 16 031b 16 031c 16 031d 16 031e 16 031f 16 0320 16 0321 16 0322 16 0323 16 0324 16 0325 16 0326 16 0327 16 0328 16 0329 16 032a 16 032b 16 032c 16 032d 16 032e 16 032f 16 0330 16 0331 16 0332 16 0333 16 0334 16 0335 16 0336 16 0337 16 0338 16 0339 16 033a 16 033b 16 033c 16 033d 16 033e 16 033f 16 02c0 16 02c1 16 02c2 16 02c3 16 02c4 16 02c5 16 02c6 16 02c7 16 02c8 16 02c9 16 02ca 16 02cb 16 02cc 16 02cd 16 02ce 16 02cf 16 02d0 16 02d1 16 02d2 16 02d3 16 02d4 16 02d5 16 02d6 16 02d7 16 02d8 16 02d9 16 02da 16 02db 16 02dc 16 02dd 16 02de 16 02df 16 02e0 16 02e1 16 02e2 16 02e3 16 02e4 16 02e5 16 02e6 16 02e7 16 02e8 16 02e9 16 02ea 16 02eb 16 02ec 16 02ed 16 02ee 16 02ef 16 02f0 16 02f1 16 02f2 16 02f3 16 02f4 16 02f5 16 02f6 16 02f7 16 02f8 16 02f9 16 02fa 16 02fb 16 02fc 16 02fd 16 02fe 16 02ff 16 x0 register (x0r) y0 register (y0r) x1 register (x1r) y1 register (y1r) x2 register (x2r) y2 register (y2r) x3 register (x3r) y3 register (y3r) x4 register (x4r) y4 register (y4r) x5 register (x5r) y5 register (y5r) x6 register (x6r) y6 register (y6r) x7 register (x7r) y7 register (y7r) x8 register (x8r) y8 register (y8r) x9 register (x9r) y9 register (y9r) x10 register (x10r) y10 register (y10r) x11 register (x11r) y11 register (y11r) x12 register (x12r) y12 register (y12r) x13 register (x13r) y13 register (y13r) x14 register (x14r) y14 register (y14r) x15 register (x15r) y15 register (y15r) xy control register (xyc) uart4 special mode register (u4smr) uart4 receive buffer register (u4rb) uart4 transmit buffer register (u4tb) uart4 transmit/receive control register 0 (u4c0) uart4 transmit/receive mode register (u4mr) uart4 transmit/receive control register 1 (u4c1) uart4 bit rate generator (u4brg) uart4 special mode register 2 (u4smr2) timer a1-1 register (ta11) timer a2-1 register (ta21) dead time timer(dtt) timer b2 interrupt occurrence frequency set counter(ictb2) three-phase pwm control register 0(invc0) three-phase pwm control register 1(invc1) thrree-phase output buffer register 0(idb0) thrree-phase output buffer register 1(idb1) timer b3 register (tb3) timer b4 register (tb4) timer b5 register (tb5) timer b3, 4, 5 count start flag (tbsr) timer b3 mode register (tb3mr) timer b4 mode register (tb4mr) timer b5 mode register (tb5mr) interrupt cause select register (ifsr) uart2 special mode register (u2smr) uart2 receive buffer register (u2rb) uart2 transmit buffer register (u2tb) uart2 transmit/receive control register 0 (u2c0) uart2 transmit/receive mode register (u2mr) uart2 transmit/receive control register 1 (u2c1) uart2 bit rate generator (u2brg) timer a4-1 register (ta41) uart2 special mode register 2 (u2smr2) uart3 special mode register (u3smr) uart3 receive buffer register (u3rb) uart3 transmit buffer register (u3tb) uart3 transmit/receive control register 0 (u3c0) uart3 transmit/receive mode register (u3mr) uart3 transmit/receive control register 1 (u3c1) uart3 bit rate generator (u3brg) uart3 special mode register 2 (u3smr2) uart4 special mode register 3 (u4smr3) uart2 special mode register 3 (u2smr3) uart3 special mode register 3 (u3smr3) (the blank area is reserved and cannot be used by user.)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer sfr 22 figure 1.5.3. location of peripheral unit control registers (3) 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 0360 16 0361 16 0362 16 0363 16 0364 16 0365 16 0366 16 0367 16 0368 16 0369 16 036a 16 036b 16 036c 16 036d 16 036e 16 036f 16 0370 16 0371 16 0372 16 0373 16 0374 16 0375 16 0376 16 0377 16 0378 16 0379 16 037a 16 037b 16 037c 16 037d 16 037e 16 037f 16 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 timer a0 register (ta0) timer a1 register (ta1) timer a2 register (ta2) timer b0 register (tb0) timer b1 register (tb1) timer b2 register (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 register (ta3) timer a4 register (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) clock prescaler reset flag (cpsrf) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) crc data register (crcd) crc input register (crcin) uart transmit/receive control register 2 (ucon2) a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) function select register c(psc) function select register a1 (ps1) function select register a0 (ps0) function select register b0 (psl0) function select register b1 (psl1) function select register a3 (ps3) function select register a2 (ps2) function select register b2 (psl2) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) dma3 request cause select register (dm3sl) dma2 request cause select register (dm2sl) function select register b3 (psl3) flash memory control register 0 (fmr0) (note) flash memory control register 1 (fmr1) (note) note :this register exists in the flash memory version. (the blank area is reserved and cannot be used by user.)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer sfr 23 figure 1.5.4. location of peripheral unit control registers (4) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port p0 (p0) port p0 direction register (pd0) port p1 (p1) port p1 direction register (pd1) port p2 (p2) port p2 direction register (pd2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p5 direction register (pd5) port p6 (p6) port p6 direction register (pd6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) pull-up control register 2 (pur2) port control register (pcr) pull-up control register 3 (pur3) port p11 (p11) port p11 direction register (pd11) port p12 (p12) port p12 direction register (pd12) port p13 (p13) port p13 direction register (pd13) port p14 (p14) port p14 direction register (pd14) port p15 (p15) port p15 direction register (pd15) pull-up control register 4 (pur4) (the blank area is reserved and cannot be used by user.)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer software reset 24 software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software) reset to the microcomputer. a software reset has the same effect as a hardware reset. the contents of internal ram are preserved. processor mode (1) types of processor mode one of three processor modes can be selected: single-chip mode, memory expansion mode, and micro- processor mode. the functions of some pins, the memory map, and the access space differ according to the selected processor mode. ? single-chip mode in single-chip mode, only internal memory space (sfr, internal ram, and internal rom) can be accessed. ports p0 to p10 can be used as programmable i/o ports or as i/o ports for the internal peripheral functions. ? memory expansion mode in memory expansion mode, external memory can be accessed in addition to the internal memory space (sfr, internal ram, and internal rom). in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) ? microprocessor mode in microprocessor mode, the sfr, internal ram, and external memory space can be accessed. the internal rom area cannot be accessed. in this mode, some of the pins function as the address bus, the data bus, and as control signals. the number of pins assigned to these functions depends on the bus and register settings. (see bus settings for details.) (2) setting processor modes the processor mode is set using the cnv ss pin and the processor mode bits (bits 1 and 0 at address 0004 16 ). do not set the processor mode bits to 10 2 . regardless of the level of the cnv ss pin, changing the processor mode bits selects the mode. therefore, never change the processor mode bits when changing the contents of other bits. also do not attempt to shift to or from the microprocessor mode within the program stored in the internal rom area. ? applying v ss to cnv ss pin the microcomputer begins operation in single-chip mode after being reset. memory expansion mode is selected by writing 01 2 to the processor mode is selected bits. ? applying v cc to cnv ss pin the microcomputer starts to operate in microprocessor mode after being reset. figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1. figure 1.6.3 shows the memory maps applicable for each processor modes.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 25 processor mode figure 1.6.1. processor mode register 0 processor mode register 0 (note 1) symbol address when reset pm0 0004 16 80 16 (note 2) bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: single-chip mode 0 1: memory expansion mode 1 0: inhibited 1 1: microprocessor mode b1 b0 pm03 pm01 pm00 processor mode bit pm02 r/w mode select bit (note 7) 0 : rd,bhe,wr 1 : rd,wrh,wrl software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. pm04 0 0 : multiplexed bus is not used 0 1 : allocated to cs2 space 1 0 : allocated to cs1 space 1 1 : allocated to entire space (note4) b5 b4 multiplexed bus space select bit (note 3) pm05 pm07 bclk output disable bit (note 5) 0 : bclk is output (note 6) 1 : function set by bit 0,1 of system clock control register 0 note 1: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. note 2: if the v cc voltage is applied to the cnv ss , the value of this register when reset is 03 16 . (pm00 is set to ??and pm07 is set to ??) note 3: valid in microprocessor and memory expansion modes 1, 2 and 3. do not use multiplex bus when mode 0 is selected. do not set to allocated to cs2 space when mode 2 is selected. note 4: after the reset has been released, the m16c/80 group mcu operates using the separate bus. as a result, in microprocessor mode, you cannot select the full cs space multiplex bus. when you select the full cs space multiplex bus in memory expansion mode, the address bus operates with 64 kbytes boundaries for each chip select. mode 0: multiplexed bus cannot be used. mode 1: cs0 to cs2 when you select full cs space. mode 2: cs0 to cs1 when you select full cs space. mode 3: cs0 to cs3 when you select full cs space. note 5: no bclk is output in single chip mode even when "0" is set in pm07. when stopping clock output in microprocessor or memory expansion mode, make the following settings: pm07="1", bit 0 (cm00) and bit 1 (cm01) of system clock control register 0 (address 0006 16 ) = "0". "l" is now output from p5 3 . note 6: when selecting bclk, set bits 0 and 1 of system clock control register 0 (cm00, cm01) to "0". note 7: when using 16-bit bus width in dram controler, set this bit to "1". w r a aa a aa a aa a aa a aa a aa a a aa aa a aa reserved bit must always be set to 0 0
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 26 processor mode figure 1.6.2. processor mode register 1 processor mode register 1 (note 1) :flash memory version symbol address when reset pm1 0005 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note 1: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. note 2: when mode 3 is selected, dramc is not used. note 3: valid in memory expansion mode or in microprocessor mode. note 4: when selecting p5 3 /bclk, set bits 0 and 1 of system clock control register 0 (cm00, cm01) to "0". ale pin select bit (note 3) 0 0 : no ale 0 1 : p5 3 /bclk (note 4) 1 0 : p5 6 /ras 1 1 : p5 4 /hlda b5 b4 pm15 pm14 reserved bit must always be set to ? w r a aa a a aa aa a a aa aa aa reserved bit must always be set to 1 0 pm12 internal memory wait bit 0 : no wait state 1 : wait state inserted external memory area mode bit (note 3) 0 0 : mode 0 (p4 4 to p4 7 : a 20 to a 23 ) 0 1 : mode 1 (p4 4 : a 20 , p4 5 to p4 7 : cs2 to cs0) 1 0 : mode 2 (p4 4 , p4 5 : a 20 , a 21 , p4 6 , p4 7 : cs1, cs0) 1 1 : mode 3 (note 2) (p4 4 to p4 7 : cs3 to cs0) b1 b0 pm11 pm10 a a aa aa processor mode register 1 (note 1) :mask rom version symbol address when reset pm1 0005 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 note 1: set bit 1 of the protect register (address 000a 16 ) to 1 when writing new values to this register. note 2: when mode 3 is selected, dramc is not used. note 3: valid in memory expansion mode or in microprocessor mode. note 4: when selecting p5 3 /bclk, set bits 0 and 1 of system clock control register 0 (cm00, cm01) to "0". ale pin select bit (note 3) 0 0 : no ale 0 1 : p5 3 /bclk (note 4) 1 0 : p5 6 /ras 1 1 : p5 4 /hlda b5 b4 pm15 pm14 reserved bit must always be set to 0 w r a aa a aa aa nothing is assinged. when read, the content is indeterminate. 0 pm12 internal memory wait bit 0 : no wait state 1 : wait state inserted external memory area mode bit (note 3) 0 0 : mode 0 (p4 4 to p4 7 : a 20 to a 23 ) 0 1 : mode 1 (p4 4 : a 20 , p4 5 to p4 7 : cs2 to cs0) 1 0 : mode 2 (p4 4 , p4 5 : a 20 , a 21 , p4 6 , p4 7 : cs1, cs0) 1 1 : mode 3 (note 2) (p4 4 to p4 7 : cs3 to cs0) b1 b0 pm11 pm10 a aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 27 processor mode figure 1.6.3. memory maps in each processor mode (without memory area expansion, normal mode) singl chip mode memory expanded mode microprocesser mode sfr area internal ram area internal reserved area internal rom area no use external area cs2 2mbytes cs0 2mbytes no use internal rom area internal reserved area internal rom area internal reserved area internal rom area internal reserved area cs0 3mbytes cs1 4mbytes (note2) cs1 2mbytes (note1) external area cs2 2mbytes no use cs0 2mbytes cs0 4mbytes cs1 4mbytes (note2) 000000 16 000400 16 000800 16 200000 16 400000 16 c00000 16 e00000 16 f00000 16 ffffff 16 each cs0, cs1 and cs can set 0 to 3 wait. mode 0 mode 1 mode 2 mode 0 mode 1 mode 2 sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area internal reserved area sfr area internal ram area mode 3 internal reserved area sfr area internal ram area internal rom area internal reserved area cs1 1mbytes mode 3 internal reserved area sfr area internal ram area no use cs2 1mbytes no use connect with dram 0.05 to 8mb (when not connect with dram, use as external area.) external area connect with dram 0.05 to 8mb (when open area is under 8mb, cannot use the rest of this area.) connect with dram 0.05 to 8mb (when open area is under 8mb, cannot use the rest of this area.) connect with dram 0.05 to 8mb (when open area is under 8mb, cannot use the rest of this area.) no use (cannot use as dram area or external area.) connect with dram 0.05 to 8mb (when not connect with dram, use as external area.) connect with dram 0.05 to 8mb (when open area is under 8mb, cannot use the rest of this area.) no use (cannot use as dram area or external area.) external area no use cs3 1mbytes cs0 1mbytes cs1 1mbytes no use cs2 1mbytes no use cs1 2mbytes (note1) no use cs3 1mbytes cs0 1mbytes processor mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus settings 28 bus settings the byte pin, bit 0 to 3 of the external data bus width control register (address 000b 16 ), bits 4 and 5 of the processor mode register 0 (address 0004 16 ) and bit 0 and 1 of the processor mode register 1 (address 0005 16 ) are used to change the bus settings. table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width control register and table 1.7.2 shows external area 0 to 3 and external area mode. bus setting switching factor switching external address bus width external data bus width control register switching external data bus width byte pin (external area 3 only) switching between separate and multiplex bus bits 4 and 5 of processor mode register 0 (1) selecting external address bus width you can select the width of the address bus output externally from the 16 mbytes address space, the number of chip select signals, and the address area of the chip select signals. (note, however, that when ____ you select full cs space multiplex bus, addresses a 0 to a 15 are output.) the combination of bits 0 and 1 of the processor mode register 1 allow you to set the external area mode. when using dram controller, the dram area is output by multiplexing of the time splitting of the row and column addresses. (2) selecting external data bus width you can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. when the data bus width bit of the external data bus width control register is 0, the data bus width is 8 bits; when 1, it is 16 bits. the width can be set for each of the external areas. the default bus width for external area 3 is 16 bits when the byte pin is l after a reset, or 8 bits when the byte pin is h after a reset. the bus width selection is valid only for the external bus (the internal bus width is always 16 bits). during operation, fix the level of the byte pin to h or l. (3) selecting separate/multiplex bus the bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0. ? separate bus in this bus configuration, input and output is performed on separate data and address buses. the data bus width can be set to 8 bits or 16 bits using the external data bus width control register. for all programmable external areas, p0 is the data bus when the external data bus is set to 8 bits, and p1 is a programmable io port. when the external data bus width is set to 16 bits for any of the external areas, p0 and p1 (although p1 is undefined for any 8-bit bus areas) are the data bus. when accessing memory using the separate bus configuration, you can select a software wait using the wait control register. ? multiplex bus in this bus configuration, data and addresses are input and output on a time-sharing basis. for areas for which 8-bit has been selected using the external data bus width control register, the 8 bits d0 to d7 are multiplexed with the 8 bits a0 to a7. for areas for which 16-bit has been selected using the external data bus width control register, the 16 bits d0 to d15 are multiplexed with the 16 bits a0 to a15. when accessing memory using the multiplex bus configuration, two waits are inserted regard- less of whether you select no wait or 1 wait in the appropriate bit of the wait control register. table 1.7.1. factors for switching bus settings
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus settings 29 ____ the default after a reset is the separate bus configuration, and the full cs space multiplex bus configu- ____ ration cannot be selected in microprocessor mode. if you select full cs space multiplex bus, the 16 bits from a0 to a15 are output for the address external data bus width control register symbol address when reset ds 000b 16 xxxxx000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ds3 ds1 ds0 external area 0 data bus width bit ds2 external area 1 data bus width bit external area 2 data bus width bit external area 3 data bus width bit (note) 0 : 8 bits data bus width 1 : 16 bits data bus width note: the value after a reset is determined by the input via the byte pin. w r a a a a a a a a nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width 0 : 8 bits data bus width 1 : 16 bits data bus width figure 1.7.1. external data bus width control register note 1: dramc area when using dramc. note 2: set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register 1 (address 0005 16 ). external area mode (note 2) mode 0 mode 1 mode 2 mode 3 external area 0 external area 1 external area 2 external area 3 memory expansion mode memory expansion mode , microprocessor mode microprocessor mode memory expansion mode , microprocessor mode 008000 16 to 1fffff 16 200000 16 to 3fffff 16 400000 16 to bfffff 16 (note 1) c00000 16 to efffff 16 c00000 16 to ffffff 16 008000 16 to 1fffff 16 200000 16 to 3fffff 16 400000 16 to bfffff 16 c00000 16 to efffff 16 e00000 16 to ffffff 16 008000 16 to 1fffff 16 400000 16 to bfffff 16 c00000 16 to efffff 16 c00000 16 to ffffff 16 100000 16 to 1fffff 16 200000 16 to 2fffff 16 c00000 16 to cfffff 16 e00000 16 to efffff 16 f00000 16 to ffffff 16 memory expansion mode , microprocessor mode no area is selected. table 1.7.2. external area 0 to 3 and external area mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus settings 30 p0 0 to p0 7 i/o port data bus data bus data bus data bus i/o port i/o port cs1 or cs2 : multiplexed bus, and the other : separate bus separate bus all space multiplexed bus single-chip mode memory expansion mode/microprocessor modes memory expansion mode data bus width byte pin level ?1? ?0 ?0 ?1?(note 1) all external area is 8 bits some external area is 16 bits all external area is 8 bits some external area is 16 bits note 1:the default after a reset is the separate bus configuration, and "full cs space multiplex bus" cannot be selected in microprocessor mode. when you select "full cs space multiplex bus" in extended memory mode, the address bus operates with 64 kbytes boundaries for each chip select. note 2: address bus in separate bus configuration. note 3: the ale output pin is selected using bits 4 and 5 of the processor mode register 1. note 4: when you have selected use of the dram controller and you access the dram area, these are casl, cash, dw, and bclk outputs. note 5: the cs signal and address bus selection are set by the external area mode. processor mode multiplexed bus space select bit cs (chip select) or address bus (a 23 ) (for details, refer to ?us control? (note 5) outputs rd, wrl, wrh, and bclk or rd, bhe, wr, and bclk (for details, refer to ?us control? (note 3,4) p1 0 to p1 7 i/o port i/o port data bus i/o port data bus i/o port i/o port p2 0 to p2 7 i/o port address bus address bus address bus address bus address bus address bus /data bus /data bus /data bus /data bus p4 0 to p4 3 i/o port address bus address bus address bus address bus i/o port i/o port p4 4 to p4 6 i/o port cs (chip select) or address bus (a 23 ) (for details, refer to ?us control? (note 5) p4 7 i/o port p5 0 to p5 3 i/o port p5 4 i/o port hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) hlda(note 3) p5 5 i/o port hold hold hold hold hold hold p5 6 i/o port ras (note 3) ras (note 3) ras (note 3) ras (note 3) ras (note 3) ras (note 3) p5 7 i/o port rdy rdy rdy rdy rdy rdy p3 0 to p3 7 i/o port address bus address bus address bus address bus address bus address bus /data bus /data bus (note 2) (note 2) (note 2) table 1.7.3. each processor mode and port function
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 31 bus control the following explains the signals required for accessing external devices and software waits. the signals required for accessing the external devices are valid when the processor mode is set to memory expansion mode and microprocessor mode. (1) address bus/data bus ____ ____ there are 24 pins, a 0 to a 22 and a 23 for the address bus for accessing the 16 mbytes address space. a 23 is an inverted output of the msb of the address. the data bus consists of pins for data io. the external data bus control register (address 000b 16 ) selects the 8-bit data bus, d0 to d7 for each external area, or the 16-bit data bus, d0 to d15. after a reset, there is by default an 8-bit data bus for the external area 3 when the byte pin is h, or a 16-bit data bus when the byte pin is l. when shifting from single-chip mode to extended memory mode, the value on the address bus is unde- fined until an external area is accessed. when accessing a dram area with dram control in use, a multiplexed signal consisting of row address and column address is output to a 8 to a 20 . (2) chip select signals ____ the chip select signals share a 0 to a 22 and a 23 . you can use bits 0 and 1 of the processor mode register 1 (address 0005 16 ) to set the external area mode, then select the chip select area and number of address outputs. in microprocessor mode, external area mode 0 is selected after a reset. the external area can be split into a maximum of four using the chip select signals. table 1.7.4 shows the external areas specified by the chip select signals. table 1.7.4. external areas specified by the chip select signals processor mode memory space expansion mode specified address range memory expansion mode mode 0 chip select signal cs0 cs1 cs2 cs3 c00000 16 to dfffff 16 (2 mbytes) microprocessor mode memory expansion mode 008000 16 to 1fffff 16 (2016 kbytes) 200000 16 to 3fffff 16 (2 mbytes) 008000 16 to 3fffff 16 (4064 kbytes) microprocessor mode e00000 16 to ffffff 16 (2 mbytes) c00000 16 to efffff 16 (3 mbytes) c00000 16 to ffffff 16 (4 mbytes) e00000 16 to efffff 16 (1 mbytes) 100000 16 to 1fffff 16 (1 mbytes) mode 1 mode 2 mode 3 memory expansion mode microprocessor mode f00000 16 to ffffff 16 (1 mbytes) 200000 16 to 2fffff 16 (1 mbytes) c00000 16 to cfffff 16 (1 mbytes) (a22) (a21) (a20) (a23) (a21) (a20) (a20)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 32 _____ ______ ________ table 1.7.6. operation of rd, wr, and bhe signals status of external data bus rd bhe wr hll lhl hlh lhh write 1 byte of data to odd address read 1 byte of data from odd address write 1 byte of data to even address read 1 byte of data from even address data bus width a0 h h l l hll l lhl l hl h / l lh h / l 8-bit write data to both even and odd addresses read data from both even and odd addresses write 1 byte of data read 1 byte of data 16-bit not used not used status of external data bus read data write 1 byte of data to even address write 1 byte of data to odd address write data to both even and odd addresses wrh wrl rd data bus width 16-bit h h h h l h l h h l l l h h (note) l (note) l not used write 1 byte of data read 1 byte of data not used 8-bit (3) read/write signals with a 16-bit data bus, bit 2 of the processor mode register 0 (address 0004 16 ) select the combinations of _____ ________ ______ _____ ________ _________ rd, bhe, and wr signals or rd, wrl, and wrh signals. with a 8-bit full space data bus, use the _____ ______ ________ combination of rd, wr, and bhe signals as read/write signals. (set "0" to bit 2 of the processor mode register 0 (address 0004 16 ).) when using both 8-bit and 16-bit data bus widths and you access an 8-bit _____ ______ ________ data bus area, the rd, wr and bhe signals combination is selected regardless of the value of bit 2 of the processor mode register 0 (address 0004 16 ). tables 1.7.5 and 1.7.6 show the operation of these signals. _____ ______ ________ after a reset has been cancelled, the combination of rd, wr, and bhe signals is automatically selected. _____ _________ _________ when switching to the rd, wrl, and wrh combination, do not write to external memory until bit 2 of the processor mode register 0 (address 0004 16 ) has been set (note). note 1: before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register (address 000a 16 ) to 1. _____ ________ _________ note 2: when using 16-bit data bus width for dram controller, select rd, wrl, and wrh signals. _____ ________ _________ table 1.7.5. operation of rd, wrl, and wrh signals ______ note: it becomes wr signal.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 33 (4) ale signal the ale signal latches the address when accessing the multiplex bus space. latch the address when the ale signal falls. the ale output pin is selected using bits 4 and 5 of the processor mode register 1 (address 0005 16 ). the ale signal is occurred regardless of internal area and external area. figure 1.7.2. ale signal and address/data bus (5) ready signal the ready signal facilitates access of external devices that require a long time for access. as shown in ________ figure 1.7.2, inputting l to the rdy pin at the falling edge of bclk causes the microcomputer to enter ________ the ready state. inputting h to the rdy pin at the falling edge of bclk cancels the ready state. table _____ 1.7.7 shows the microcomputer status in the ready state. figure 1.7.3 shows the example of the rd ________ signal being extended using the rdy signal. ready is valid when accessing the external area during the bus cycle in which the software wait is ap- ________ plied. when no software wait is operating, the rdy signal is ignored, but even in this case, unused pins must be pulled up. table 1.7.7. microcomputer status in ready state (note) item status oscillation on _____ _____ _____ rd/wr signal, address bus, data bus, cs maintain status when ready signal received __________ ale signal, hlda, programmable i/o ports internal peripheral circuits on note: the ready signal cannot be received immediately prior to a software wait. when byte pin = ? when byte pin = ? ale address data (note 1) address d 0 /a 0 to d 7 /a 7 a 8 to a 15 ale address data (note 1) address (note 2) d 0 /a 0 to d 15 /a 15 a 16 to a 19 note 1: floating when reading. note 2: when full space multiplexed bus is selected, these are i/o ports. address (note 2) address or cs a 20 to a 22 , a 23 address or cs a 20 to a 22 , a 23 a 16 to a 19
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 34 _____ ________ figure 1.7.3. example of rd signal extended by rdy signal rdy received timing aa separate bus (2 wait) multiplexed bus (2 wait) bclk rd cs i (i=0 to 3) rdy aaaaaa aaaaaa bclk rd cs i (i=0 to 3) rdy tsu(rdy - bclk) aaaaaaaa aaaaaaaa 1st cycle 2nd cycle 3rd cycle 4th cycle tsu(rdy - bclk) rdy received timing input rdy signal at i + 1 cycles for i wait. (i = 1 to 3) 1st cycle 2nd cycle 3rd cycle 4th cycle : wait using rdy signal : wait using software (note) (note) note: chip select may get longer by a state of cpu such as an instruction queue buffer.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 35 item status oscillation on _____ _____ _____ _______ rd/wr signal, address bus, data bus, cs, bhe floating programmable i/o ports p0, p1, p2, p3, p4, p5 m aintains status when hold signal is received p6, p7, p8, p9, p10 __________ hlda output l internal peripheral circuits on (but watchdog timer stops) ale signal undefined (7) external bus status when accessing to internal area table 1.7.9 shows external bus status when accessing to internal area table 1.7.9. external bus status when accessing to internal area (6) hold signal the hold signal is used to transfer the bus privileges from the cpu to the external circuits. inputting l to __________ the hold pin places the microcomputer in the hold state at the end of the current bus access. this status __________ __________ is maintained and l is output from the hlda pin as long as l is input to the hold pin. table 1.7.8 shows the microcomputer status in the hold state. the bus is used in the following descending order of __________ priority: hold, dmac, cpu. _____ ________ figure 1.7.4. example of rd signal extended by rdy signal __________ hold > dmac > cpu table 1.7.8. microcomputer status in hold state item sfr accessing status internal rom/ram accessing status address bus remain address of external area accessed immediately before data bus when read floating when write floating _____ ______ ________ _________ rd, wr, wrl, wrh output "h" ________ bhe remain external area status accessed immediately before ____ cs output "h" ale ale output (8) bclk output bclk output can be selected by bit 7 of the processor mode register 0 (address 0004 16 :pm07) and bit 1 and bit 0 of the system clock select register 0 (address 0006 16 :cm01, cm00). setting pm07 to 0 and cm01 and cm00 to 00 2 outputs the bclk signal from p5 3 . however, in single chip mode, bclk signal is not output. when setting pm07 to 1, the function is as set by cm01 and cm00.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 36 (10) software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note) and bits 4 to 7 of the wait control register (address 0008 16 ). figure 1.7.5 shows wait control register you can use the external area i wait bits (where i = 0 to 3) of the wait control register to specify from no wait to 3 waits for the external memory area. when you select no wait, the read cycle is executed in the bclk1 cycle. the write cycle is executed in the bclk2 cycle (which has 1 wait). when accessing external memory using the multiplex bus, access has two waits regardless of whether you specify no wait or 1 wait in the appropriate external area i wait bits in the wait control register. software waits in the internal memory (internal ram and internal rom) can be set using the internal memory wait bits of the processor mode register 1 (address 0005 16 ). setting the internal memory wait bit = 0 sets no wait. setting the internal memory wait bit = 1 specifies a wait. the sfr area is not affected by the setting of the internal memory wait bit and is always accessed in the bclk2 cycle. table 1.7.11 shows the software waits and bus cycles. figures 1.7.6 and 1.7.7 show example bus timings when using software waits. status of external data bus ras cash casl lll lll lhh lll read data from both even and odd addresses read 1 byte of data from even address read 1 byte of data from odd address write data to both even and odd addresses data bus width dw h h h l llhl lhl l ll h ll l 8-bit write 1 byte of data to even address write 1 byte of data to odd address read 1 byte of data write 1 byte of data 16-bit not used not used _______ __________ __________ _____ (9) dram controller signals (ras, casl, cash, and dw) bits 1, 2, and 3 of the dram control register (address 0004 16 ) select the dram space and enable the dram controller. the dram controller signals are then output when the dram area is accessed. table 1.7.10 shows the operation of the respective signals. _______ __________ __________ _____ table 1.7.10. operation of ras, casl, cash, and dw signals
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 37 area bus status internal memory wait bit external memory area i wait bit bus cycle 1 2 bclk cycles external memory area 00 2 read :1 bclk cycle separate bus write : 2 bclk cycles 2 bclk cycles 3 bclk cycles multiplex bus 4 bclk cycles sfr internal rom/ram 0 1 bclk cycle 2 bclk cycles 3 bclk cycle 3 bclk cycles 3 bclk cycles 4 bclk cycles 01 2 11 2 00 2 01 2 11 2 10 2 10 2 table 1.7.11. software waits and bus cycles figure 1.7.5. wait control register wait control register symbol address when reset wcr 0008 16 ff 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0: without wait 0 1: with 1 wait 1 0: with 2 wait 1 1: with 3 wait b1 b0 wcr wcr1 wcr0 external area 0 wait bit wcr2 external area 1 wait bit external area 2 wait bit wcr4 external area 3 wait bit wcr5 wcr7 note 1: when using the multiplex bus configuration, there are two waits regardless of whether you have specified "no wait" or "1 wait". however, you can specify "2 wait" or "3 wait". note 2: when using the separate bus configuration, the read bus cycle is executed in the bclk1 cycle, and the write cycle is executed in the bclk2 cycle (with 1 wait). w r a a a a a a a a a a a a a a a a a a wcr6 0 0: without wait 0 1: with 1 wait 1 0: with 2 wait 1 1: with 3 wait b3 b2 0 0: without wait 0 1: with 1 wait 1 0: with 2 wait 1 1: with 3 wait b5 b4 0 0: without wait 0 1: with 1 wait 1 0: with 2 wait 1 1: with 3 wait b7 b6
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 38 figure 1.7.6. typical bus timings using software wait output input address address bus cycle (note) < separate bus (with wait) > bclk read signal write signal data bus address bus (note 2) chip select (note 2,3) bclk read signal data bus chip select (note 2,3) data output address address bus (note 2) address input < separate bus with 2 wait > write signal bclk read signal write signal address bus (note 2) address bus cycle (note) < separate bus (no wait) > output data bus chip select (note 2,3) input bus cycle (note) bus cycle (note) bus cycle (note 1) bus cycle (note 1) address note 1: this timing example shows bus cycle length. read cycle and write cycle may be continued after this bus cycle. note 2: address bus and chip select may get longer by a state of cpu such as an instruction queue buffer. note 3: when accessing same external area (same cs area) continuously, chip select may output continuously.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer bus control 39 figure 1.7.7. typical bus timings using software wait bclk read signal write signal address bus/data bus (note 2) chip select (note 2,3) address address address data output address address input ale bus cycle (note) < multiplexed bus (with 2 wait) > bus cycle (note) bclk read signal write signal chip select (note 2,3) bus cycle (note) < separate bus (with 3 wait) > address address (note 2) address bus cycle (note) data bus data output input bclk read signal write signal address bus /data bus (note 2) chip select (note 2,3) address address data output address input bus cycle (note) < multiplexed bus (with 3 wait) > address address ale bus cycle (note) note 1: this timing example shows bus cycle length. read cycle and write cycle may be continued after this bus cycle. note 2: address bus and chip select may get longer by a state of cpu such as an instruction queue buffer. note 3: when accessing same external area (same cs area) continuously, chip select may output continuously.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 40 figure 1.8.2. examples of sub clock table 1.8.1. main clock and sub clock generating circuits clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. example of oscillator circuit figure 1.8.1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure 1.8.2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures 1.8.1 and 1.8.2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. figure 1.8.1. examples of main clock main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x c in , x cout oscillation stop/restart function available available oscillator status immediately after reset oscillating stopped other externally derived clock can be input microcomputer (built-in feedback resistance) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistance) x in x out r d c in c out (note) note: insert a damping resistance if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. insert a feedback resistance between x in and x out when an oscillation manufacture required. microcomputer (built-in feedback resistance) x cin x cout externally derived clock open vcc vss note: insert a damping resistance if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. insert a feedback resistance between x cin and x cout when an oscillation manufacture required. microcomputer (built-in feedback resistance) x cin x cout (note) c cin c cout r cd
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 41 clock control figure 1.8.3 shows the block diagram of the clock generating circuit. sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r nmi interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaaa aaaa divider 1 a d 1/2 1/2 1/2 1/2 a details of divider 1 x in f 8 f 32 c b b 1/2 c f 32 sio2 f 8 sio2 f 1 sio2 bclk aaaa aaaa divider 2 1/n divider a details of divider 2 e n is set by mcd4 to mcd0 as follow: n = 1, 2, 3, 4, 6, 8, 10, 12, 14 and 16 e figure 1.8.3. clock generating circuit
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 42 the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). switching to the sub clock oscillation as cpu operating clock source before stopping the clock reduces the power dissipation. when the main clock is stoped (bit 5 at address 0006 16 =1) or the mode is shifted to stop mode (bit 0 at address 0007 16 =1), the main clock division register (address 000c 16 ) is set to the division by 8 ("08 16 "). after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit defaults to 1 when shifting from high-speed or middle-speed mode to stop mode and after a reset. this bit remains in low-speed and low power dissipation mode. (2) sub clock the sub clock is generated by the sub clock oscillation circuit. no sub clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub clock oscillation has fully stabilized before switching. after the oscillation of the sub clock oscillation circuit has stabilized, the drive capacity of the sub clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is either fc or is derived by dividing the main clock by 1, 2, 3, 4, 6, 8, 10, 12, 14 or 16. the bclk is derived by dividing the main clock by 8 after a reset. this signal is output from bclk pin using cm01, cm00 and pm07 in memory expansion mode and microprocessor mode. when main clock is stoped or shifting to stop mode, the main clock division register (address 000c 16 ) is set to the division by 8 ("08 16 "). (4) peripheral function clock ? f 1 , f 8 , f 32 , f 1sio2 , f 8sio2 , f 32sio2 the clock for the peripheral devices is derived from the main clock or by dividing it by 8 or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. ? f ad this clock has the same frequency as the main clock and is used for a-d conversion. (5) f c32 this clock is derived by dividing the sub clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub clock. it is used for bclk and for the watchdog timer. figure 1.8.4 shows the system clock control registers 0 and 1 and figure 1.8.5 shows main clock division register.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 43 figure 1.8.4. clock control registers 0 and 1 system clock control register 0 (note 1) symbol address when reset cm0 0006 16 08 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 3 0 1 : f c output (note 3) 1 0 : f 8 output (note 3) 1 1 : f 32 output (note 3) b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 clock output function select bit (note 2) wait peripheral function clock stop bit 0 : do not stop f 1 , f 8 , f 32 in wait mode 1 : stop f 1 , f 8 , f 32 in wait mode x cin -x cout drive capacity select bit (note 4) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 5, 6) 0 : on 1 : off (note 7) system clock select bit (note 9) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: when outputting bclk (bit 7 of processor mode register 0 is "0"), set these bits to "00". when outputting ale to p5 3 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". the port p5 3 function is not selected even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". note 3: when selecting f c , f 8 or f 32 in single chip mode, must use p5 7 as input port. note 4: changes to ??when shifting to stop mode or reset. note 5: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? note 6: when this bit is "1", x out is "h". also, the internal feedback resistance remains on, so x in is pulled up to x out ("h" level) via the feedback resistance. note 7: when the main clock is stopped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. note 8: when "1" has been set once, "0" cannot be written by software. note 9: to set cm07 "1" from "0", first set cm04 to "1", and an oscillation of sub clock is stable. then set cm07. do not set cm04 and cm07 simultaneously. also, to set cm07 "0" from "1", first set cm05 to "1", and an oscillation of main clock is stable. then set cm07. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note 3) 0 : clock on 1 : all clocks off (stop mode) (note 4) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shifting from high-speed or middle-speed mode to stop mode or reset. this bit is remained in low speed or low power dissipation mode. note 3: when this bit is "1", x out is "h", and the internal feedback resistance is disabled. x cin and x cout are high-inpedance. note 4: when the main clock is stopped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r reserved bit always set to ? 0 0 0 0 a a aa aa a a aa aa a aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a a aa aa a aa a aa reserved bit always set to 0 a aa 00 cm06 watchdog timer function select bit 0 : watchdog timer interrupt 1 : reset (note 8)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 44 figure 1.8.5. main clock division register main clock division register (note 1) symbol address when reset mcd 000c 16 xxx01000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 0 : no division mode 0 0 0 1 0 : division by 2 mode 0 0 0 1 1 : division by 3 mode 0 0 1 0 0 : division by 4 mode 0 0 1 1 0 : division by 6 mode 0 1 0 0 0 : division by 8 mode 0 1 0 1 0 : division by 10 mode 0 1 1 0 0 : division by 12 mode 0 1 1 1 0 : division by 14 mode 0 0 0 0 0 : division by 16 mode b4 b3 b2 b1 b0 mcd4 mcd3 mcd1 mcd2 mcd0 main clock division select bit (note 2) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: these bits are "01000 2 " (8-division mode) when main clock is stopped or you shift to stop mode. note 3: do not attempt to set combinations of values other than those shown in this figure. w r a aa a aa a aa a aa a aa nothing is assigned. when write, set "0". when read, their contents are indeterminate. clock output in single chip mode, when the bclk output function select bit (bit 7 at address 0004 16 :pm07) is 1, you can output f 8 , f 32 , or fc from the p5 3 /bclk/ale/clk out pins by setting the clock output function select bits (bits 1 and 0 at address 0006 16 :cm01, cm00).(note) even when you set pm07 to 0 and cm01 and cm00 to 00 2 , no bclk is output. in memory expansion mode or microprocessor mode, when the ale pin select bits (bits 5 and 4 at ad- dress 0005 16 :pm15, pm14) are other than 01 2 (p5 3 /bclk) and pm07 is 1, you can output f 8 , f 32 , or fc from the p5 3 /bclk/ale/clk out pins by setting cm01 and cm00. in memory expansion mode or microprocessor mode, when pm15 and pm14 are other than 01 2 (p5 3 / bclk) and pm07 is 0 and cm01 and cm00 to 00 2 , bclk is output from the p5 3 /bclk/ale/clk out pins. when stopping clock output in memory expansion mode or microprocessor mode, set pm07 to 1 and cm01 and cm00 to 00 2 (io port p5 3 ). the p5 3 function is not selected. when pm15 and pm14 are 01 2 (p5 3 /bclk) and cm01 and cm00 are 00 2 , pm07 is ignored and the p5 3 pin is set for ale output. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, f 8 or f 32 clock output is stopped when a wait command is executed. table 1.8.2 shows clock output setting (single chip mode) and table 1.8.3 shows clock output setting (memory expansion/microprocessor mode). note :when outputting the f 8 , f 32 or fc from port p5 3 /bclk/ale/clk out pin in single chip mode, use port _______ p5 7 /rdy as an input only port.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock generating circuit 45 table 1.8.2. clock output setting (single chip mode) pm07 cm01 cm00 pm14 p5 3 /bclk/ale/clk out pin function 0/1 1 1 1 0 0 1 1 ignored ignored ignored ignored ignored ignored ignored ignored pm15 p5 3 i/o port fc output f 8 output f 32 output bclk output function select bit clock output function select bit ale pin select bit 0 1 0 1 note :must use p5 7 as input port. (note) (note) (note) table 1.8.3. clock output setting (memory expansion/microprocessor mode) 0 1 1 1 0 0 0 1 1 1 0 1 0 0 bclk output "l" output (not p5 3 ) fc output f 8 output 0 0 1 0 11 0 0 1 f 32 output ale output 1 0 pm07 cm01 cm00 pm14 p5 3 /bclk/ale/clk out pin function ignored pm15 bclk output function select bit clock output function select bit ale pin select bit stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation of bclk, f 1 to f 32 , f 1sio2 to f 32sio2 , fc, fc 32 , and f ad stops in stop mode, peripheral functions such as the a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uarti(i = 0 to 2) functions provided an external clock is selected. table 1.8.4 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or interrupt. when using an interrupt to exit stop mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits (bits 2, 1, and 0 at address 009f 16 ) for exiting a stop/wait state. set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (flg) processor interrupt level (ipl). figure 1.8.6 shows the exit priority register. when exiting stop mode using an interrupt, the relevant interrupt routine is executed. when shifting to stop mode and reset, the main clock division register (000c 16 ) is set to 08 16 .
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 46 pin memory expansion mode single-chip mode microprocessor mode _______ _______ address bus, data bus, cs0 to cs3 retains status before stop mode _____ ______ ________ ________ _________ ___ _________ rd, wr, bhe, wrl, wrh, w, casl, h (note) ________ cash ________ ras h (note) __________ hlda, bclk h ale h port retains status before stop mode retains status before stop mode clk out when fc selected h h when f 8 , f 32 selected retains status before stop mode retains status before stop mode ________ ________ note :when self-refresh is done in operating dram control, cas and ras becomes l. table 1.8.4. port status during stop mode figure 1.8.6. exit priority register exit priority register symbol address when reset rlvl 009f 16 xxxx0000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : level 0 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 fsit rlvl1 rlvl2 rlvl0 interrupt priority set bit for exiting stop/wait state (note 1,2) note 1: exits the stop or wait mode when the requested interrupt priority level is higher than that set in the exit priority register. note 2: set to the same value as the processor interrupt priority level (ipl) set in the flag register (flg). note 3: the high-speed interrupt can only be specified for interrupts with interrupt priority level 7. specify interrupt priority level 7 for only one interrupt. w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0: interrupt priority level 7 = normal interrupt 1: interrupt priority level 7 = high-speed interrupt high-speed interrupt set bit (note 3) a a a a a a a a a a clock generating circuit
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 47 table 1.8.5. port status during wait mode pin memory expansion mode single-chip mode microprocessor mode _______ _______ address bus, data bus, cs0 to cs3, retains status before wait mode ________ bhe _____ ______ ________ _________ ______ _________ rd, wr, wrl, wrh, dw, casl, h (note) ________ cash ________ ras h (note) __________ hlda,bclk h ale l port retains status before wait mode retains status before wait mode clk out when f c selected does not stop when f 8 , f 32 selected does not stop when the wait peripheral function clock stop bit is 0. when the wait peripheral function clock stop bit is 1, the status immediately prior to entering wait mode is main- tained. ________ ________ note :when self-refresh is done in operating dram control, cas and ras becomes l. wait mode when a wait instruction is executed, the bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but the bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table 1.8.5 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts using as bclk the clock that had been selected when the wait instruction was executed. when using an interrupt to exit wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exiting a stop/wait state (bits 2, 1, and 0 at address 009f 16 ). set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (flg) processor interrupt level (ipl). when using an interrupt to exit wait mode, the microcomputer resumes operating the clock that was oper- ating when the wait command was executed as bclk from the interrupt routine. wait mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 48 status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table 1.8.6 shows the operating modes corresponding to the settings of system clock control registers 0 and main clock division register. after a reset, operation defaults to division by 8 mode. when shifting to stop mode, reset or stopping main clock, the main clock division register (address 000c 16 ) is set to 08 16 . (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 3 mode the main clock is divided by 3 to obtain the bclk. (3) division by 4 mode the main clock is divided by 4 to obtain the bclk. (4) division by 6 mode the main clock is divided by 6 to obtain the bclk. (5) division by 8 mode the main clock is divided by 8 to obtain the bclk. after reset, this mode is executed. note that oscillation of the main clock must have stabilized before transferring from this mode to no-division, division by 2, 6, 10, 12, 14 and 16 mode. oscillation of the sub clock must have stabilized before transferring to low-speed and low power dissipa- tion mode. (6) division by 10 mode the main clock is divided by 10 to obtain the bclk. (7) division by 12 mode the main clock is divided by 12 to obtain the bclk. (8) division by 14 mode the main clock is divided by 14 to obtain the bclk. (9) division by 16 mode the main clock is divided by 16 to obtain the bclk. (10) no-division mode the main clock is divided by 1 to obtain the bclk. (11) low-speed mode f c is used as bclk. note that oscillation of both the main and sub clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (12) low power dissipation mode f c is the bclk and the main clock is stopped. when the main clock is stoped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. bclk status
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 49 0 0 invalid 1 0 0 1 0 no division 0 0 invalid 0 0 0 1 0 division by 2 mode 0 0 invalid 0 0 0 1 1 division by 3 mode 0 0 invalid 0 0 1 0 0 division by 4 mode 0 0 invalid 0 0 1 1 0 division by 6 mode 0 0 invalid 0 1 0 0 0 division by 8 mode 0 0 invalid 0 1 0 1 0 division by 10 mode 0 0 invalid 0 1 1 0 0 division by 12 mode 0 0 invalid 0 1 1 1 0 division by 14 mode 0 0 invalid 0 0 0 0 0 division by 16 mode 1 0 1 invalid invalid invalid invalid invalid low-speed mode 1 1 1 invalid invalid invalid invalid invalid low power dissipation mode cm07 cm05 cm04 mcd4 mcd3 mcd2 mcd1 mcd0 operating mode of bclk table 1.8.6. operating modes dictated by settings of system clock control register 0 and main clock division register bclk status note: when count source of bclk is changed from clock a to clock b (x in to x cin or x cin to x in ), clock b needs to be stable before changing. please wait to change modes until after oscillation has stabilized.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 50 power saving in power save modes, the cpu and oscillator stop and the operating clock is slowed to minimize power dissipation by the cpu. the following outlines the power save modes. there are three power save modes. (1) normal operating mode ? high-speed mode in this mode, one main clock cycle forms bclk. the cpu operates on the selected internal clock. the peripheral functions operate on the clocks specified for each respective function. ? medium-speed mode in this mode, the main clock is divided into 2, 3, 4, 6, 8, 10, 12, 14, or 16 to form bclk. the cpu operates on the selected internal clock. the peripheral functions operated on the clocks specified for each respective function. ? low-speed mode in this mode, fc forms bclk. the cpu operates on the fc clock. fc is the clock supplied by the subclock. the peripheral functions operate on the clocks specified for each respective function. ? low power-dissipation mode this mode is selected when the main clock is stopped from low-speed mode. the cpu operates on the fc clock. fc is the clock supplied by the subclock. only the peripheral functions for which the subclock was selected as the count source continue to run. (2) wait mode cpu operation is halted in this mode. the oscillator continues to run. (3) stop mode all oscillators stop in this mode. the cpu and internal peripheral functions all stop. of all 3 power saving modes, power savings are greatest in this mode. figure 1.8.7 shows the clock transition between each of the three modes, (1), (2), and (3). power saving
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 51 figure 1.8.7. clock transition wait mode cpu operation stopped cm10=? transition of stop mode, wait mode bclk :f(x in )/8 cm07=?? mcd=?8 16 main clock is oscillating sub clock is oscillating main clock is oscillating sub clock is stopped note 1: switch clocks after oscillation of main clock is fully stable. note 2: switch clocks after oscillation of sub clock is fully stable. note 3: set the desired division to the main clock division register (mcd). note 4: when shifting to division by 8 mode, mcd is set to "08 16 ". main clock is oscillating sub clock is stopped cm04=? mcd=?x 16 ? note 1, 3 cm04=? bclk :f(x in ) /division rate cm07=?? mcd=?x 16 note 4 bclk :f(x in ) cm07=?? mcd=?2 16 high-speed mode medium-speed mode (divided-by-2, 3, 4, 6, 8, 10, 12, 14 and 16 mode) bclk :f(x in ) /division rate cm07=?? mcd=?x 16 note 4 bclk :f(x in ) cm07=?? mcd=?2 16 high-speed mode medium-speed mode (divided-by-2, 3, 4, 6, 10, 12, 14 and 16 mode) medium-speed mode (divided-by-8 mode) transition of normal mode normal mode cm10=? stop mode all oscillators stopped wait mode cpu operation stopped cm04=? cm05=?? note 4 bclk :f(x cin ) cm07=? low-speed mode bclk :f(x cin ) cm07=? main clock is oscillating sub clock is oscillating mcd=?x 16 ? note 1, 3 cm07=? note 1 mcd=?x 16 ? note 3 cm07=? note 2 cm10=? stop mode all oscillators stopped wait mode cpu operation stopped (please see the following as transition of normal mode.) cm07=?? note 1 mcd=?x 16 ? note 3 cm04=?? interrupt wait instruction interrupt wait instruction interrupt wait instruction interrupt interrupt interrupt low power dissipation mode cm05=? high-speed/medium- speed mode low-speed/low power dissipation mode medium-speed mode (divided-by-8 mode) note 1 note 2 note 1 note 1: switch clocks after oscillation of main clock is fully stable. after stop mode or when main clock oscillation is stopp ed, transferred to the middle speed mode. note 2: switch clocks after oscillation of sub clock is fully stable. note 3: the main ckock devision register is set to the division by 8 mode (mcd="08 16 "). note 4: when shifting to low power dissipation mode, the main ckock devision register is set to the division by 8 mode (mcd="08 16 "). please change according to a direction of an arrow. cm07=?? note 2 cm05=? high-speed/medium-speed mode low-speed/low power dissipation mode main clock is stopped sub clock is oscillating reset note 4 note 3 power saving
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 52 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure 1.8.8 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), system clock control register 1 (address 0007 16 ), main clock division register (address 000c 16 ), port p9 direction register (address 03c7 16 ) and function select register a3 (address 03b5 16 ) can only be changed when the respective bit in the protect register is set to 1. therefore, impor- tant outputs can be allocated to port p9. if, after 1 (write-enabled) has been written to the prc2 (bit 2 at address 000a 16 ), a value is written to any address, the bit automatically reverts to 0 (write-inhibited). change port p9 input/output and function select register a3 immediately after setting "1" to prc2. interrupt and dma transfer should not be inserted between instructions. however, the prc0 (bit 0 at address 000a 16 ) and prc1 (bit 1 at address 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. protect register symbol address when reset prcr 000a 16 xxxxx000 2 bit name bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 : write-inhibited 1 : write-enabled prc1 prc0 prc2 enables writing to processor mode registers 0 and 1 (addresses 0004 16 and 0005 16 ) function 0 : write-inhibited 1 : write-enabled enables writing to system clock control registers 0 and 1 (addresses 0006 16 and 0007 16 ) and main clock division register (address 0008 16 ) enables writing to port p9 direction register (address 03c7 16 ) and function select register a3 (address 03b5 16 ) (note ) 0 : write-inhibited 1 : write-enabled w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. note: writing a value to an address after ??is written to this bit returns the bit to ?? other bits do not automatically return to ??and they must therefore be reset b y the p ro g ram. a a a a a a figure 1.8.8. protect register protection
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 53 undefined instruction (und instruction) overflow (into instruction) brk instruction brk2 instruction int instruction ? ? ? y ? ? ? t ? y ? t software hardware interrupt ? y ? t ? ? y ? t reset _______ nmi watchdog timer single step address matched special peripheral i/o *1 figure 1.9.1. classification of interrupts *1 peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. high-speed interrupt can be used as highest priority in peripheral i/o interrupts. interrupt outline types of interrupts figure 1.9.1 lists the types of interrupts. ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 54 software interrupts software interrupts are generated by some instruction that generates an interrupt request when ex- ecuted. software interrupts are nonmaskable interrupts. (1) undefined-instruction interrupt this interrupt occurs when the und instruction is executed. (2) overflow interrupt this interrupt occurs if the into instruction is executed when the o flag is 1. the following lists the instructions that cause the o flag to change: abs, adc, adcf, add, addx, cmp, cmpx, div, divu, divx, neg, rmpa, sbb, scmpu, sha, sub, subx (3) brk interrupt this interrupt occurs when the brk instruction is executed. (4) brk2 interrupt this interrupt occurs when the brk2 instruction is executed. this interrupt is used exclusively for debugger purposes. you normally do not need to use this interrupt. (5) int instruction interrupt this interrupt occurs when the int instruction is executed after specifying a software interrupt number from 0 to 63. note that software interrupt numbers 0 to 43 are assigned to peripheral i/o interrupts. this means that by executing the int instruction, you can execute the same interrupt routine as used in peripheral i/o interrupts. the stack pointer used in int instruction interrupt varies depending on the software interrupt number. for software interrupt numbers 0 to 31, the u flag is saved when an interrupt occurs and the u flag is cleared to 0 to choose the interrupt stack pointer (isp) before executing the interrupt sequence. the previous u flag before the interrupt occurred is restored when control returns from the interrupt rou- tine. for software interrupt numbers 32 to 63, such stack pointer switchover does not occur. however, in peripheral i/o interrupts, the u flag is saved when an interrupt occurs and the u flag is cleared to 0 to choose isp. therefore movement of u flag is different by peripheral i/o interrupt or int instruction in software interrupt number 32 to 43.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 55 hardware interrupts there are two types in hardware interrupts; special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are nonmaskable interrupts. ? reset ____________ a reset occurs when the reset pin is pulled low. ______ ? nmi interrupt ______ this interrupt occurs when the nmi pin is pulled low. ? watchdog timer interrupt this interrupt is caused by the watchdog timer. ? address-match interrupt this interrupt occurs when the program's execution address matches the content of the address match register while the address match interrupt enable bit is set (= 1). this interrupt does not occur if any address other than the start address of an instruction is set in the address match register. ? single-step interrupt this interrupt is used exclusively for debugger purposes. you normally do not need to use this inter- rupt. a single-step interrupt occurs when the d flag is set (= 1); in this case, an interrupt is generated each time an instruction is executed. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 43 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? bus collision detection, start/stop condition detection interrupts (uart2, uart3, uart4), fault error interrupts (uart3, 4) this is an interrupt that the serial i/o bus collision detection generates. when i 2 c mode is selected, _____ start, stop condition interrupt is selected. when ss pin is selected, fault error interrupt is selected. ? dma0 through dma3 interrupts these are interrupts that dma generates. ? key-input interrupt ___ a key-input interrupt occurs if an l is input to the ki pin. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0, uart1, uart2/nack, uart3/nack and uart4/nack transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0, uart1, uart2/ack, uart3/ack and uart4/ack reception interrupt these are interrupts that the serial i/o reception generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b5 interrupt these are interrupts that timer b generates. _______ ________ ? int0 interrupt through int5 interrupt _____ _____ an int interrupt selects a edge sense or a level sense. in edge sense, an int interrupt occurs if either _____ _____ a rising edge or a falling edge or a both edge is input to the int pin. in level sense, an int interrupt _____ occurs if either a "h" level or a "l" level is input to the int pin.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 56 figure 1.9.2. format for specifying interrupt vector addresses aaaaaaaaa aaaaaaaaa mid address aaaaaaaaa aaaaaaaaa low address aaaaaaaaa aaaaaaaaa high address aaaaaaaaa aaaaaaaaa 0 0 0 0 0 0 0 0 vector address + 0 vector address + 1 vector address + 2 vector address + 3 lsb msb high-speed interrupts high-speed interrupts are interrupts in which the response is executed at 5 cycles and the return is 3 cycles. when a high-speed interrupt is received, the flag register (flg) and program counter (pc) are saved to the save flag register (svf) and save pc register (svp) and the program is executed from the address shown in the vector register (vct). execute a freit instruction to return from the high-speed interrupt routine. high-speed interrupts can be set by setting 1 in the high-speed interrupt specification bit allocated to bit 3 of the exit priority register. setting 1 in the high-speed interrupt specification bit makes the interrupt set to level 7 in the interrupt control register into a high-speed interrupt. you can only set one interrupt as a high-speed interrupt. when using a high-speed interrupt, do not set multiple interrupts as level 7 interrupts. the interrupt vector for a high-speed interrupt must be set in the vector register (vct). when using a high-speed interrupt, you can use a maximum of two dmac channels. the execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. in this case, switch register bank mode for high-speed interrupt routine. interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure 1.9.2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 57 interrupt source vector table addresses remarks address (l) to address (h) undefined instruction ffffdc 16 to ffffdf 16 interrupt on und instruction overflow ffffe0 16 to ffffe3 16 interrupt on into instruction brk instruction ffffe4 16 to ffffe7 16 if content of ffffe7 16 is filled with ff 16 , program execution starts from the address shown by the vector in the variable vector table address match ffffe8 16 to ffffeb 16 there is an address-matching interrupt enable bit watchdog timer fffff0 16 to fffff3 16 _______ nmi fffff8 16 to fffffb 16 _______ external interrupt by input to nmi pin reset fffffc 16 to ffffff 16 table 1.9.1. interrupt factors (fixed interrupt vector addresses) interrupt source vector table addresses remarks address (l) to address (h) brk2 instruction interrupt vector table register for emulator interrupt for debugger 000020 16 to 000023 16 single step interrupt vector table register for emulator interrupt for debugger 000020 16 to 000023 16 table 1.9.2. interrupt vector table register for emulator ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from ffffdc 16 to ffffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table 1.9.1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. ? vector table dedicated for emulator table 1.9.2 shows interrupt vector address which is vector table register dedicated for emulator (ad- dress 000020 16 to 000023 16 ). these instructions are not effected with interrupt enable flag (i flag) (non maskable interrupt). this interrupt is used exclusively for debugger purposes. you normally do not need to use this inter- rupt. do not access to the interrupt vector table register dedicated for emulator (address 000020 16 to 000023 16 ). ? variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table 1.9.3 shows the interrupts assigned to the variable vector tables and addresses of vector tables. set an even address to the start address of vector table setting in intb so that operating efficiency is increased.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 58 table 1.9.3. interrupt causes (variable interrupt vector addresses) software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note 1) brk instruction software interrupt number 0 +44 to +47 (note 1) software interrupt number 11 +48 to +51 (note 1) software interrupt number 12 +52 to +55 (note 1) software interrupt number 13 +56 to +59 (note 1) software interrupt number 14 +68 to +71 (note 1) software interrupt number 17 +72 to +75 (note 1) software interrupt number 18 +76 to +79 (note 1) software interrupt number 19 +80 to +83 (note 1) software interrupt number 20 +84 to +87 (note 1) software interrupt number 21 +88 to +91 (note 1) software interrupt number 22 +92 to +95 (note 1) software interrupt number 23 +96 to +99 (note 1) software interrupt number 24 +100 to +103 (note 1) software interrupt number 25 +104 to +107 (note 1) software interrupt number 26 +108 to +111 (note 1) software interrupt number 27 +112 to +115 (note 1) software interrupt number 28 +116 to +119 (note 1) software interrupt number 29 +120 to +123 (note 1) software interrupt number 30 +124 to +127 (note 1) software interrupt number 31 +128 to +131 (note 1) software interrupt number 32 +252 to +255 (note 1) software interrupt number 63 to note 1: address relative to address in interrupt table register (intb). note 2: when i c mode is selected, nack/ack, start/stop condition detection interrupts are selected. note 3: the fault error interrupt is selected when ss pin is selected. cannot be masked i flag +40 to +43 (note 1) software interrupt number 10 +60 to +63 (note 1) software interrupt number 15 +64 to +67 (note 1) software interrupt number 16 +32 to +35 (note 1) software interrupt number 8 +36 to +39 (note 1) software interrupt number 9 timer b3 timer b4 timer b5 int3 to dma0 dma1 timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 int0 int1 int2 software interrupt int4 int5 bus collision detection, start/stop condition detection (uart2) (note 2) uart0 transmit uart0 receive uart1 transmit uart1 receive key input interrupt a-d uart2 transmit/nack (note 2) uart2 receive/ack (note 2) dma2 dma3 uart3 transmit/nack (note 2) uart3 receive/ack (note 2) uart4 transmit/nack (note 2) uart4 receive/ack (note 2) bus collision detection, start/stop condition detection, fault error (uart3) (note 2, 3) bus collision detection, start/stop condition detection, fault error (uart4) (note 2, 3) +132 to +135 (note 1) software interrupt number 33 +136 to +139 (note 1) software interrupt number 34 +140 to +143 (note 1) software interrupt number 35 +144 to +147 (note 1) software interrupt number 36 +148 to +151 (note 1) software interrupt number 37 +152 to +155 (note 1) software interrupt number 38 +156 to +159 (note 1) software interrupt number 39 +160 to +163 (note 1) software interrupt number 40 +164 to +167 (note 1) software interrupt number 41 +168 to +171 (note 1) software interrupt number 42 +172 to +175 (note 1) software interrupt number 43 +176 to +179 (note 1) software interrupt number 44 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 59 interrupt control registers peripheral i/o interrupts have their own interrupt control registers. figure 1.9.3 shows the interrupt con- trol registers. when using an interrupt to exit stop mode or wait mode, the relevant interrupt must have been enabled and set to a priority level above the level set by the interrupt priority set bits for exit a stop/wait state (bits 2, 1, and 0 at address 009f 16 ). set the interrupt priority set bits for the exit from a stop/wait state to the same level as the flag register (flg) processor interrupt level (ipl). figure 1.9.4 shows the exit priority register.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 60 figure 1.9.3. interrupt control register symbol address when reset intiic(i=0 to 5) 009e 16 , 007e 16 , 009c 16 , 007c 16 , 009a 16 , 007a 16 xx00x000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a ilvl0 ir pol nothing is assigned. when write, set "0". when read, their contents are indeterminate. interrupt priority level select bit interrupt request bit polarity select bit level sense/edge sense select bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge or l level 1 : selects rising edge or h level ilvl1 ilvl2 note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: when int3 to int5 are used for data bus in microprocessor mode or memory expansion mode, set the interrupt disabled to int3ic, int4ic and int5ic. note 3: when level sense is selected, set related bit of interrupt cause select register ( address 031f 16 ) to one edge. (note 1) interrupt control register b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a aa aa a a bit name function bit symbol w r symbol address when reset adic 0073 16 xxxxx000 2 bcniic(i=2 to 4) 008f 16 , 0071 16 , 0091 16 xxxxx000 2 dmiic(i=0 to 3) 0068 16 , 0088 16 , 006a 16 , 008a 16 xxxxx000 2 kupic 0093 16 xxxxx000 2 taiic(i=0 to 4) 006c 16 , 008c 16 , 006e 16 , 008e 16, 0070 16 xxxxx000 2 tbiic(i=0 to 5) 0094 16 , 0076 16 , 0096 16 , 0078 16 , 0098 16 , 0069 16 xxxxx000 2 sitic(i=0 to 4) 0090 16 , 0092 16 , 0089 16 , 008b 16 , 008d 16 xxxxx000 2 siric(i=0 to 4) 0072 16 , 0074 16 , 006b 16 , 006d 16 , 006f 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. when write, set "0". when read, their contents are indeterminate. (note) note: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa 0 : edge sense 1 : level sense lvs (note 2) (note 3)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 61 figure 1.9.4. exit priority register exit priority register symbol address when reset rlvl 009f 16 xxxx0000 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 : level 0 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 fsit rlvl1 rlvl2 rlvl0 interrupt priority set bit for exiting stop/wait state (note 1,2) note 1: exits the stop or wait mode when the requested interrupt priority level is higher than that set in the exit priority register. note 2: set to the same value as the processor interrupt priority level (ipl) set in the flag register (flg). note 3: the high-speed interrupt can only be specified for interrupts with interrupt priority level 7. specify interrupt priority level 7 for only one interrupt. w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. 0: interrupt priority level 7 = normal interrupt 1: interrupt priority level 7 = high-speed interrupt high-speed interrupt set bit (note 3) a a aa aa a aa a aa a a aa aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 62 interrupt enable flag (i flag) the interrupt enable flag (i flag) is used to disable/enable maskable interrupts. when this flag is set (= 1), all maskable interrupts are enabled; when the flag is cleared to 0, they are disabled. this flag is automatically cleared to 0 after a reset is cleared. interrupt request bit this bit is set (= 1) by hardware when an interrupt request is generated. the bit is cleared to 0 by hardware when the interrupt request is acknowledged and jump to the interrupt vector. this bit can be cleared to 0 (but cannot be set to 1) in software. interrupt priority level select bit and processor interrupt priority level (ipl) interrupt priority levels are set by the interrupt priority select bit in an interrupt control register. when an interrupt request is generated, the interrupt priority level of this interrupt is compared with the processor interrupt priority level (ipl). this interrupt is enabled only when its interrupt priority level is greater than the processor interrupt priority level (ipl). this means that you can disable any particu- lar interrupt by setting its interrupt priority level to 0. table 1.9.4 shows how interrupt priority levels are set. table 1.9.5 shows interrupt enable levels in relation to the processor interrupt priority level (ipl). the following lists the conditions under which an interrupt request is acknowledged: ? interrupt enable flag (i flag) = 1 ? interrupt request bit = 1 ? interrupt priority level > processor interrupt priority level (ipl) the interrupt enable flag (i flag), interrupt request bit, interrupt priority level select bit, and the proces- sor interrupt priority level (ipl) all are independent of each other, so they do not affect any other bit. 0 1 0 0 1 1 1 1 0 1 1 1 0 0 1 0 0 0 low high 1 0 1 1 1 0 1 1 1 0 0 0 1 0 0 0 0 1 0 1 0 0 1 1 table 1.9.5 ipl and interrupt enable levels table 1.9.4 interrupt priority levels interrupt priority level select bit interrupt priority level priority order b0 b1 b2 1 0 0 1 0 1 processor interrupt priority level (ipl) enabled interrupt priority levels ipl 1 ipl 0 i nterrupt levels 1 and above are enabled. interrupt levels 2 and above are enabled. interrupt levels 3 and above are enabled. interrupt levels 4 and above are enabled. interrupt levels 5 and above are enabled. interrupt levels 6 and above are enabled. interrupt levels 7 and above are enabled. all maskable interrupts are disabled. level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 ipl 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 63 rewrite the interrupt control register when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gen- erated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the scmpu, sin, smovb, smovf, smovu, sstr, sout or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading address 000000 16 (address 000002 16 when high-speed interrupt). after this, the related interrupt request bit is "0". (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt se- quence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note 1) within the cpu in the stack area. saves in the flag save register (svf) in high-speed interrupt. (5) saves the content of the program counter (pc) in the stack area. saves in the pc save register (svp) in high-speed interrupt. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure 1.9.5 shows the interrupt response time.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 64 figure 1.9.5 interrupt response time time (a) varies with each instruction being executed. the divx instruction requires a maximum time that consists of 29* cycles. time (b) is shown in table 1.9.6. * it is when the divisor is immediate or register. when the divisor is memory, the following value is added. ? normal addressing : 2 + x ? index addressing : 3 + x ? indirect addressing : 5 + x + 2y ? indirect index addressing : 5 + x + 2y x is number of wait of the divisor area. y is number of wait of the indirect address stored area. when x and y are in odd address or in 8 bits bus area, double the value of x and y. (a) the period from the occurrence of an interrupt to the completion of the instruction under execution. (b) the time required for executing the interrupt sequence. (a) (b) time instruction interrupt response time instruction in interrupt routine interrupt sequence interrupt request acknowledged interrupt request generated
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 65 table 1.9.6 interrupt sequence execution time 8 bits data bus 16 cycles 16 cycles 14 cycles 14 cycles 15 cycles 16 cycles 19 cycles 19 cycles 21 cycles 16 bits data bus 14 cycles 16 cycles 12 cycles 14 cycles 13 cycles 14 cycles 17 cycles 19 cycles 19 cycles interrupt vector address even address odd address (note 1) even address odd address (note 1) even address (note 2) even address (note 2) even address odd address (note 1) even address (note 2) vector table is internal register note 1: allocate interrupt vector addresses in even addresses as must as possible. note 2: the vector table is fixed to even address. note 3: the high-speed interrupt is independent of these conditions. interrupt peripheral i/o int instruction _______ nmi watchdog timer undefined instruction address match overflow brk instruction (variable vector table) single step brk2 instruction brk instruction (fixed vector table) high-speed interrupt (note 3) 5 cycles value that is set to ipl 7 0 not changed changes of ipl when interrupt request acknowledged when an interrupt request is acknowledged, the interrupt priority level of the acknowledged interrupt is set to the processor interrupt priority level (ipl). if an interrupt request is acknowledged that does not have an interrupt priority level, the value shown in table 1.9.7 is set to the ipl. table 1.9.7 relationship between interrupts without interrupt priority levels and ipl interrupt sources without interrupt priority levels _______ watchdog timer, nmi reset other
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 66 saving registers in an interrupt sequence, only the contents of the flag register (flg) and program counter (pc) are saved to the stack area. the order in which these contents are saved is as follows: first, the flg register is saved to the stack area. next, the 16 high-order bits and 16 low-order bits of the program counter expanded to 32-bit are saved. figure 1.9.6 shows the stack status before an interrupt request is acknowledged and the stack status after an interrupt request is acknowledged. in a high-speed interrupt sequence, the contents of the flag register (flg) is saved to the flag save register (svf) and program counter (pc) is saved to pc save register (svp). if there are any other registers you want to be saved, save them in software at the beginning of the interrupt routine. the pushm instruction allows you to save all registers except the stack pointer (sp) by a single instruction. the execution speed is improved when register bank 1 is used with high speed interrupt register selected by not saving registers to the stack but to the switching register bank. in this case, switch register bank mode for high-speed interrupt routine. [sp] stack pointer value before interrupt occurs stack status before interrupt request is acknowledged address stack status after interrupt request is acknowledged figure 1.9.6 stack status before and after an interrupt request is acknowledged m-6 m-5 mC4 mC3 mC2 mC1 m m+1 lsb msb lsb msb address stack area stack area flag register (flg l ) program counter (pc h ) flag register (flg h ) content of previous stack content of previous stack content of previous stack content of previous stack program counter (pc l ) program counter (pc m ) [sp] new stack pointer value m-6 m-5 mC4 mC3 mC2 mC1 m m+1 0 0
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 67 interrupt priority if two or more interrupt requests are sampled active at the same time, whichever interrupt request is acknowledged that has the highest priority. maskable interrupts (peripheral i/o interrupts) can be assigned any desired priority by setting the inter- rupt priority level select bit accordingly. if some maskable interrupts are assigned the same priority level, the interrupt that a request came to most in the first place is accepted at first, and then, the priority between these interrupts is resolved by the priority that is set in hardware. certain nonmaskable interrupts such as a reset (reset is given the highest priority) and watchdog timer interrupt have their priority levels set in hardware. figure 1.9.7 lists the hardware priority levels of these interrupts. software interrupts are not subjected to interrupt priority. they always cause control to branch to an interrupt routine whenever the relevant instruction is executed. interrupt resolution circuit interrupt resolution circuit selects the highest priority interrupt when two or more interrupt requests are sampled active at the same time. figure 1.9.8 shows the interrupt resolution circuit. _______ reset > nmi > watchdog > peripheral i/o > single step > address match return from interrupt routine as you execute the reit instruction at the end of the interrupt routine, the contents of the flag register (flg) and program counter (pc) that have been saved to the stack area immediately preceding the interrupt sequence are automatically restored. in high-speed interrupt, as you execute the freit instruc- tion at the end of the interrupt routine, the contents of the flag register (flg) and program counter (pc) that have been saved to the save registers immediately preceding the interrupt sequence are automati- cally restored. then control returns to the routine that was under execution before the interrupt request was acknowl- edged, and processing is resumed from where control left off. if there are any registers you saved via software in the interrupt routine, be sure to restore them using an instruction (e.g., popm instruction) before executing the reit or freit instruction. when switching the register bank before executing reit and freit instruction, switched to the register bank immediately before the interrupt sequence. figure 1.9.7. interrupt priority that is set in hardware
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 68 figure 1.9.8. interrupt resolution circuit timer b2 timer b0 timer a0 timer a1 timer b1 uart1 reception uart0 reception uart2 reception/ack a-d conversion bus collision/start, stop condition(uart2) uart1 transmission uart0 transmission uart2 transmission/nack key input interrupt processor interrupt priority level (ipl) interrupt enable flag (i flag) int5 int2 int0 watchdog timer reset dbc nmi interrupt request accepted. to cpu level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) int3 address match timer b4 timer b3 dma0 dma1 dma2 dma3 timer a2 timer a3 timer a4 int4 int1 timer b5 uart3 reception/ack uart3 transmission/nack uart4 reception/ack uart4 transmission/nack bus collision/start, stop condition/fault error (uart3) bus collision/start, stop condition/fault error (uart4) instruction fetch stop/wait return interrupt level (rlvl) interrupt request accepted. to clk
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 69 ______ int interrupts ________ ________ int0 to int5 are external input interrupts. the level sense/edge sense switching bits of the interrupt control register select the input signal level and edge at which the interrupt can be set to occur on input signal level and input signal edge. the polarity bit selects the polarity. with the external interrupt input edge sense, the interrupt can be set to occur on both rising and falling edges by setting the inti interrupt polarity switch bit of the interrupt request select register (address 031f 16 ) to 1. when you select both edges, set the polarity switch bit of the corresponding interrupt control register to the falling edge (0). when you select level sense, the inti interrupt polarity switch bit of the interrupt request select register (address 031f 16 ) to 0. figure 1.9.9 shows the interrupt request select register. figure 1.9.9 interrupt request cause select register interrupt request cause select register bit name fumction bit symbol w r symbol address when reset ifsr 031f 16 xx000000 2 ifsr0 b7 b6 b5 b4 b3 b2 b1 b0 a aa aa a int0 interrupt polarity swiching bit (note) 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges 0 : one edge 1 : two edges int1 interrupt polarity swiching bit (note) int2 interrupt polarity swiching bit (note) int3 interrupt polarity swiching bit (note) int4 interrupt polarity swiching bit (note) int5 interrupt polarity swiching bit (note) 0 : one edge 1 : two edges ifsr1 ifsr2 ifsr3 ifsr4 ifsr5 aa aa a a aa aa a a aa a aa a aa a aa a nothing is assigned. when write, set "0". when read, their contents are indeterminate. note :when level sense is selected, set this bit to "0".
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 70 interrupt control circuit key input interrupt control register (address 0093 16 ) key input interrupt request p10 7 /ki 3 p10 6 /ki 2 p10 5 /ki 1 p10 4 /ki 0 port p10 4 -p10 7 pull-up select bit port p10 7 direction register pull-up transistor port p10 7 direction register port p10 6 direction register port p10 5 direction register port p10 4 direction register pull-up transistor pull-up transistor pull-up transistor figure 1.9.10. block diagram of key input interrupt ______ nmi interrupt ______ ______ ______ an nmi interrupt is generated when the input to the p8 5 /nmi pin changes from h to l. the nmi interrupt is a non-maskable external interrupt. the pin level can be checked in the port p8 5 register (bit 5 at address 03c4 16 ). this pin cannot be used as a normal port input. notes: ______ ______ ______ when not intending to use the nmi function, be sure to connect the nmi pin to v cc (pulled-up). the nmi interrupt is non-maskable. because it cannot be disabled, the pin must be pulled up. key input interrupt if the direction register of any of p10 4 to p10 7 is set for input and a falling edge is input to that port, a key input interrupt is generated. a key input interrupt can also be used as a key-on wakeup function for cancel- ling the wait mode or stop mode. however, if you intend to use the key input interrupt, do not use p10 4 to p10 7 as a-d input ports. figure 1.9.10 shows the block diagram of the key input interrupt. note that if an l level is input to any pin that has not been disabled for input, inputs to the other pins are not detected as an interrupt. setting the key input interrupt disable bit (bit 7 at address 03af 16 ) to 1 disables key input interrupts from occurring regardless of the setting in the interrupt control register. when 1 is set in the key input interrupt disable register, there is no input via the port pin even when the direction register is set to input.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 71 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. four address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). figure 1.9.11 shows the address match interrupt-related registers. set the start address of an instruction to the address match interrupt register. address match interrupt is not generated when address such as the middle of instruction or table data is set. bit name bit symbol symbol address when reset aier 0009 16 xxxxxx00 2 address match interrupt enable register function w r aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa a aaaaaaaaaaaa a aaaaaaaaaaaaaa address match interrupt 0 enable bit 0 : interrupt disabled 1 : interrupt enabled aier0 address match interrupt 1 enable bit aier1 aaaaaaaaaaaaaa aaaaaaaaaaaaaa symbol address when reset rmad0 0012 16 to 0010 16 000000 16 rmad1 0016 16 to 0014 16 000000 16 rmad2 001a 16 to 0018 16 000000 16 rmad3 001e 16 to 001c 16 000000 16 nothing is assigned. when write, set "0". when read, their contents are indeterminate. b7 b6 b5 b4 b3 b2 b1 b0 w r address setting register for address match interrupt function values that can be set address match interrupt register i (i = 0, 1) 000000 16 to ffffff 16 0 : interrupt disabled 1 : interrupt enabled b0 b7 b0 (b16) b7 b0 (b15) (b8) b7 (b23) aa a aa a aa a aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa address match interrupt 2 enable bit 0 : interrupt disabled 1 : interrupt enabled aier2 address match interrupt 3 enable bit aier3 0 : interrupt disabled 1 : interrupt enabled aa a aa aa a a figure 1.9.11. address match interrupt-related registers
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 72 precautions for interrupts (1) reading addresses 000000 16 and 000002 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence from address 000000 16 . when high-speed interrupt is occurred, cpu read from address 000002 16 . the interrupt request bit of the certain interrupt will then be set to 0. however, reading addresses 000000 16 and 000002 16 by software does not set request bit to 0. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 000000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in _______ the stack pointer before accepting an interrupt. when using the nmi interrupt, initialize the stack point _______ at the beginning of a program. any interrupt including the nmi interrupt is generated immediately after executing the first instruction after reset. set an even number to the stack pointer. when an even number is set, execution efficiency is increased. set an even address to the stack pointer so that operating efficiency is increased. _______ (3) the nmi interrupt _______ ? as for the nmi interrupt pin, an interrupt cannot be disabled. connect it to the vcc pin via a resistance (pull-up) if unused. be sure to work on it. _______ ? the nmi pin also serves as p8 5 , which is exclusively input. reading the contents of the p8 register allows reading the pin value. use the reading of this pin only for establishing the pin level at the time _______ when the nmi interrupt is input. _______ ? signal of "l" level width more than 1 clock of cpu operation clock (bclk) is necessary for nmi pin. (4) external interrupt ? edge sense either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 to int 5 regardless of the cpu operation clock. ? level sense either an l level or an h level of 1 cycle of bclk + at least 200 ns width is necessary for the signal input to pins int 0 to int 5 regardless of the cpu operation clock. (when x in =20mhz and no division mode, at least 250 ns width is necessary.) ? when the polarity of the int 0 to int 5 pins is changed, the interrupt request bit is sometimes set to "1". after changing the polarity, set the interrupt request bit to "0". figure 1.9.12 shows the procedure for ______ changing the int interrupt generate factor. (5) rewrite the interrupt control register ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 73 ______ figure 1.9.12. switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) (6) address match interrupt do not set the following addresses to the address match interrupt register. 1. the start address of an interrupt instruction. 2. address of an instruction to clear an interrupt request bit of an interrupt control register or any of the next 7 instructions addresses immediately after an instruction to rewrite an interrupt priority level to a smaller value. 3. any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (i flag). 4. any of the next 3 instructions addresses immediately after an instruction to rewrite a processor inter- rupt priority level (ipl) to a smaller value. example 1) interrupt_a: ; interrupt a routine pushm r0,r1,r2,r3,a0,a1 ; <---- ???? ; example 2) mov.b #0,ta0ic ;change ta0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction nop ; 4th instruction nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction do not set address match interrupt during this period do not set address match interrupt to the start address of an interrupt instruction
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer interrupts 74 example 3) fset i ; set i flag ( interrupt enabled) nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction example 4) ldipl #0 ; rewrite ipl to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction do not set address match interrupt during this period do not set address match interrupt during this period
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer watchdog timer 75 watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. whether a watchdog timer interrupt is generated or reset is selected when an underflow occurs in the watchdog timer. watchdog timer interrupt is selected when bit 6 of the system control register 0 (address 0008 16 :cm06) is "0" and reset is selected when cm06 is "1". no value other than "1" can be written in cm06. once when reset is selected (cm06="1"), watchdog timer interrupt cannot be selected by software. when x in is selected for the bclk, bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). therefore, the watchdog timer cycle can be calculated as follows. however, errors can arise in the watchdog timer cycle due to the prescaler. when x in is selected in bclk watchdog timer cycle = when x cin is selected in bclk watchdog timer cycle = for example, when bclk is 20mhz and the prescaler division ratio is set to 16, the monitor timer cycle is approximately 26.2 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). cm06 is initialized only at reset. after reset, watchdog timer interrupt is selected. figure 1.10.1 shows the block diagram of the watchdog timer. figure 1.10.2 shows the watchdog timer- related registers. "cm06=0" watchdog timer interrupt request "cm06=1" reset bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 hold 1/2 prescaler prescaler division ratio (16 or 128) x watchdog timer count (32768) bclk prescaler division ratio (2) x watchdog timer count (32768) bclk figure 1.10.1. block diagram of watchdog timer
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer watchdog timer 76 watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit must always be set to ? 0 0 aa aa aa aa a a aa aa a a a figure 1.10.2. watchdog timer control and start registers system clock control register 0 (note 1) symbol address when reset cm0 0006 16 08 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p5 3 0 1 : f c output (note 3) 1 0 : f 8 output (note 3) 1 1 : f 32 output (note 3) b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 clock output function select bit (note 2) wait peripheral function clock stop bit 0 : do not stop f 1 , f 8 , f 32 in wait mode 1 : stop f 1 , f 8 , f 32 in wait mode x cin -x cout drive capacity select bit (note 4) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 5, 6) 0 : on 1 : off (note 7) system clock select bit (note 9) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: when outputting bclk (bit 7 of processor mode register 0 is "0"), set these bits to "00". when outputting ale to p5 3 (bit 5 and 4 of processor mode register 0 is "01"), set these bits to "00". the port p5 3 function is not selected even when you set "00" in microprocessor or memory expansion mode and bit 7 of the processor mode register 0 is "1". note 3: when selecting f c , f 8 or f 32 in single chip mode, must use p5 7 as input port. note 4: changes to ??when shifting to stop mode or reset. note 5: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? note 6: when this bit is "1", x out is "h". also, the internal feedback resistance remains on, so x in is pulled up to x out ("h" level) via the feedback resistance. note 7: when the main clock is stopped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. note 8: when "1" has been set once, "0" cannot be written by software. note 9: to set cm07 "1" from "0", first set cm04 to "1", and an oscillation of sub clock is stable. then set cm07. do not set cm04 and cm07 simultaneously. also, to set cm07 "0" from "1", first set cm05 to "1", and an oscillation of main clock is stable. then set cm07. w r aa aa a a aa aa a a aa aa a a aa aa a a aa a aa a aa a aa a cm06 watchdog timer function select bit 0 : watchdog timer interrupt 1 : reset (note 8)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 77 dmac this microcomputer has four dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac is a function that to transmit 1 data of a source address (8 bits / 16 bits) to a destination address when transmission request occurs. when using three or more dmac channels, the register bank 1 register and high-speed interrupt register are used as dmac registers. if you are using three or more dmac channels, you cannot, therefore, use high-speed interrupts. the cpu and dmac use the same data bus, but the dmac has a higher bus access privilege than the cpu, and because of the use of cycle-steeling, operations are performed at high-speed from the occurrence of a transfer request until one word (16 bits) or 1 byte (8 bits) of data have been sent. figure 1.11.1 shows the mapping of registers used by the dmac. table 1.11.1 shows dmac specifications. figures 1.11.2 to 1.11.5 show the structures of the registers used. as the registers shown in figure 1.11.1 is allocated in cpu, use ldc instruction when writing. when writing to dct2, dct3, drc2, drc3, dma2 and dma3, set register bank select flag (b flag) to "1" and use mov instruction to set r0 to r3, a0 and a1 registers. when writing to dsa2 and dsa3, set register bank select flag (b flag) to "1" and use ldc instruction to set sb and fb registers. dma mode register dma transfer count register dma transfer count reload register dma memory address register dma sfr address register dma memory address reload register dmd0 dmd1 dct0 dct1 drc0 drc1 dma0 dma1 dsa0 dsa1 dra0 dra1 dmac related register when using three or more dmac register channels the high-speed interrupt register is used as a dmac register dma2 transfer count register dma2 transfer count reload register dma2 memory address register dma2 sfr address register dct2 (r0) dct3 (r1) drc2 (r2) drc3 (r3) dma2 (a0) dma3 (a1) dsa2 (sb) dsa3 (fb) when using dma2 and dma3, use the cpu registers shown in parentheses. when using three or more dmac channels the register bank is used as a dmac register dma3 transfer count register dma3 transfer count reload register dma3 memory address register dma3 sfr address register svf dma2 memory address reload register dra2 (svp) dra1 (vct) flag save register dma3 memory address reload register figure 1.11.1. register map using dmac in addition to writing to the software dma request bit to start dmac transfer, the interrupt request signals output from the functions specified in the dma request factor select bits are also used. however, in contrast to the interrupt requests, repeated dma requests can be received, regardless of the interrupt flag. (note, however, that the number of actual transfers may not match the number of transfer requests if the dma request cycle is shorter than the dmr transfer cycle. for details, see the description of the dmac request bit.) see the description of the dmac request bit.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 78 item specification no. of channels 4 (cycle steal method) transfer memory space ? from any address in the 16 mbytes space to a fixed address (16 mbytes space) ? from a fixed address (16 mbytes space) to any address in the 1 m bytes space maximum no. of bytes transferred 128 kbytes (with 16-bit transfers) or 64 kbytes (with 8-bit transfers) dma request factors (note) ________ ________ falling edge of int0 to int3 or both edge timer a0 to timer a4 interrupt requests timer b0 to timer b5 interrupt requests uart0 to uart4 transmission and reception interrupt requests a-d conversion interrupt requests software triggers channel priority dma0 > dma1 > dma2 > dma3 (dma0 is the first priority) transfer unit 8 bits or 16 bits transfer address direction forward/fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer transfer ends when the transfer count register is "0000 16 ". ? repeat transfer when the transfer counter is "0000 16 ", the value in the transfer counter reload register is reloaded into the transfer counter and the dma transfer is continued dma interrupt request generation timing when the transfer counter register changes from "0001 16 " to "0000 16 ". dma startup ? single transfer transfer starts when dma transfer count register is more than "0001 16 " and the dma is requested after 01 2 is written to the channel i transfer mode select bits ? repeat transfer transfer starts when the dma is requested after 11 2 is written to the channel i transfer mode select bits dma shutdown ? single transfer when 00 2 is written to the channel i transfer mode select bits and dma transfer count register becomes "0000 16 " by dma transfer or write ? repeat transfer when 00 2 is written to the channel i transfer mode select bits reload timing when the transfer counter register changes from "0001 16 " to "0000 16 " in repeat transfer mode. reading / writing the register registers are always read/write enabled. number of dma transfer cycles between sfr and internal ram : 3 cycles between external i/o and external memory : minimum 3 cycles table 1.11.1. dmac specifications note: dma transfer is not effective to any interrupt.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 79 dmai request cause select register (i = 0 to 3)(note 1) symbol address when reset dmisl 0378 16 to 037b 16 0x000000 2 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 rw dsel1 dsel2 dsel3 nothing is assigned. when write, set "0". when read, the value of these bits is indeterminate. software dma request bit (note 5) if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr b4 b3 b2 b1 b0 0 0 0 0 0 : software trigger 0 0 0 0 1 : falling edge of inti pin (note 3) 0 0 0 1 0 : two edges of inti pin (note 3) 0 0 0 1 1 : timer a0 0 0 1 0 0 : timer a1 0 0 1 0 1 : timer a2 0 0 1 1 0 : timer a3 0 0 1 1 1 : timer a4 0 1 0 0 0 : timer b0 0 1 0 0 1 : timer b1 0 1 0 1 0 : timer b2 0 1 0 1 1 : timer b3 0 1 1 0 0 : timer b4 0 1 1 0 1 : timer b5 0 1 1 1 0 : uart0 transmit 0 1 1 1 1 : uart0 receive 1 0 0 0 0 : uart1 transmit 1 0 0 0 1 : uart1 receive 1 0 0 1 0 : uart2 transmit 1 0 0 1 1 : uart2 receive/ack (note 4) 1 0 1 0 0 : uart3 transmit 1 0 1 0 1 : uart3 receive/ack (note 4) 1 0 1 1 0 : uart4 transmit 1 0 1 1 1 : uart4 receive/ack (note 4) 1 1 0 0 0 : a-d conversion 1 1 0 0 1 to 1 1 1 1 1 : inhibit a a a a a a a a a a a a a a a a bit name dma request bit drq 0 : not requested 1 : requested a a note 1: please refer to dmac precautions. note 2: set dma inhibit before changing the dma request cause. set drq to "1" simultaneously. e.g.) mov.b #083h, dmisl ; set timer a0 note 3: dma0-int0, dma1-int1, dma2-int2, and dma3-int3 correspond to dmai and inti. however, when int3 pin becomes data bus in microprocessor mode, dma3- int3 cannot be used. note 4: uarti reception and ack switching are effected using the uarti special mode register and uarti special mode register 2. note 5: when setting dsr to "1", set drq to "1" using or instruction etc. simultaneously. e.g.) or.b #0a0h, dmisl note 6: do not write "0" to this bit. there is no need to clear the dma request bit. (note 5,6) (note 2) dsel4 a a a a figure 1.11.2. dmac register (1)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 80 dma mode register 0 (cpu internal register) symbol when reset dmd0 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 channel 0 transfer mode select bit md00 rw md01 bw0 rw0 md11 b1 b0 0 0 : dma inhibit 0 1 : single transfer 1 0 : reserved 1 1 : repeat transfer a aa a aa a aa a a aa aa bit name md10 channel 0 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 0 transfer direction select bit 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address channel 1 transfer mode select bit bw1 rw1 b5 b4 0 0 : dma inhibit 0 1 : single transfer 1 0 : reserved 1 1 : repeat transfer a a aa aa a aa a aa a aa channel 1 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 1 transfer direction select bit dma mode register 1 (cpu internal register) symbol when reset dmd1 00 16 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 channel 2 transfer mode select bit md20 rw md21 bw2 rw2 md31 b1 b0 0 0 : dma inhibit 0 1 : single transfer 1 0 : reserved 1 1 : repeat transfer a aa a aa a aa a aa bit name md30 channel 2 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 2 transfer direction select bit channel 3 transfer mode select bit bw3 rw3 b5 b4 0 0 : dma inhibit 0 1 : single transfer 1 0 : reserved 1 1 : repeat transfer a aa a aa a a aa aa a a aa aa channel 3 transfer unit select bit 0 : 8 bits 1 : 16 bits channel 3 transfer direction select bit 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address 0 : fixed address to memory (forward direction) 1 : memory (forward direction) to fixed address figure 1.11.3. dmac register (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 81 figure 1.11.4. dmac register (3) function rw ?transfer counter set transfer number symbol address dct0 xxxx 16 dct1 xxxx 16 dct2 (bank 1 r0) (note 1) 0000 16 dct3 (bank 1 r1) (note 1) 0000 16 dmai transfer count register (i = 0 to 3) (cpu internal register) transfer count specification 0000 16 to ffff 16 a a aa aa note 1: when setting dct2 and dct3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to r0 and r1 of register bank 1. note 2: when "0" is set to this register, data transfer is not done even if dma is requested. b15 b0 function rw transfer count register reload value set transfer number symbol address drc0 xxxx 16 drc1 xxxx 16 drc2 (bank 1 r2) (note 1) 0000 16 drc3 (bank 1 r3) (note 1) 0000 16 dmai transfer count reload register (i = 0 to 3) (cpu internal register) transfer count specification 0000 16 to ffff 16 a a aa aa note: when setting drc2 and drc3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to r2 and r3 of register bank 1. b15 b0
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 82 figure 1.11.5. dmac register (4) b23 b0 function rw ?memory address (note 2) set source or destination memory address symbol address dma0 xxxxxx 16 dma1 xxxxxx 16 dma2 (bank 1 a0) (note 1) 000000 16 dma3 (bank 1 a1) (note 1) 000000 16 dmai memory address register (i = 0, 1) (cpu internal register) transfer count specification 000000 16 to ffffff 16 (16 mbytes area) aa a note 1: when setting dma2 and dma3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to a0 and a1 of register bank 1. note 2: when the transfer direction select bit is "0" (fixed address to memory), this register is destination memory address. when the transfer direction select bit is "1" (memory to fixed address), this register is source memory address. b0 function rw sfr address (note 2) set source or destination fixed address symbol address dsa0 xxxxxx 16 dsa1 xxxxxx 16 dsa2 (bank 1 sb) (note 1) 000000 16 dsa3 (bank 1 fb) (note 1) 000000 16 dmai sfr address register (i = 0 to 3) (cpu internal register) transfer count specification 000000 16 to ffffff 16 (16 mbytes area) aa a note 1: when setting dsa2, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to sb of register bank 1. when setting dsa3, set "1" to the register bank select flag (b flag) of flag register (flg), and set desired value to fb of register bank 1. note 2: when the transfer direction select bit is "0" (fixed address to memory), this register is destination fixed address. when the transfer direction select bit is "1" (memory to fixed address), this register is source fixed address. b0 function rw memory address register reload value set source or destination memory address symbol address dra0 xxxxxx 16 dra1 xxxxxx 16 dra2 (svp) (note) xxxxxx 16 dra3 (vct) (note) xxxxxx 16 dmai memory address reload register (i = 0, 1) (cpu internal register) transfer count specification 000000 16 to ffffff 16 (16 mbytes area) aa a note: when setting dra2, set desired value to save pc register (svp). when setting dra3, set desired value to vector register (vct). b23 b23
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 83 (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. in memory expansion mode and microprocessor mode, the number of read and write bus cycles also de- pends on the level of the byte pin. also, the bus cycle itself is longer when software waits are inserted. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. (b) effect of external data bus width control register when in memory expansion mode or microprocessor mode, the transfer cycle changes according to the data bus width at the source and destination. 1. when transferring 16 bits of data and the data bus width at the source and at the destination is 8 bits (data bus width bit = 0), there are two 8-bit data transfers. therefore, two bus cycles are required for reading and two cycles for writing. 2. when transferring 16 bits of data and the data bus width at the source is 8 bits (data bus width bit = 0) and the data bus width at the destination is 16 bits (data bus width bit = 1), the data is read in two 8-bit blocks and written as 16-bit data. therefore, two bus cycles are required for reading and one cycle for writing. 3. when transferring 16 bits of data and the data bus width at the source is 16 bits (data bus width bit = 1) and the data bus width at the destination is 8 bits (data bus width bit = 0), 16 bits of data are read and written as two 8-bit blocks. therefore, one bus cycle is required for reading and two cycles for writing. (c) effect of software wait when the sfr area or a memory area with a software wait is accessed, the number of cycles is increased for the wait by 1 bus cycle. the length of the cycle is determined by bclk. figure 1.11.6 shows the example of the transfer cycles for a source read. figure 1.11.6 shows the desti- nation is external area, the destination write cycle is shown as two cycle (one bus cycle) and the source read cycles for the different conditions. in reality, the destination write cycle is subject to the same condi- tions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle. for example (2) in figure 1.11.6, if data is being transferred in 16-bit units on an 8-bit bus, two bus cycles are required for both the source read cycle and the destination write cycle.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 84 bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination (1) 8-bit transfers 16-bit transfers from even address and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source (3) one wait is inserted into the source read under the conditions in (1) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source source + 1 source + 1 (2) 16-bit transfers and the source address is odd transferring 16-bit data on an 8-bit data bus (in this case, there are also two destination write cycles). bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source source + 1 source + 1 (4) one wait is inserted into the source read under the conditions in (2) (when 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles). note: the same timing changes occur with the respective conditions at the destination as at the source. destination destination destination destination destination destination destination figure 1.11.6. example of the transfer cycles for a source read
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 85 transfer unit bus width access address no. of read no. of write no. of read no. of write cycles cycles cycles cycles 16-bit even 1111 8-bit transfers (dsi = 1) odd 1111 (bwi = 0) 8-bit even 1 1 (dsi = 0) odd 1 1 16-bit even 1111 16-bit transfers (dsi = 1) odd 2222 (bwi = 1) 8-bit even 2 2 (dsi = 0) odd 2 2 table 1.11.2. no. of dmac transfer cycles coefficient j, k (2) dmac transfer cycles any combination of even or odd transfer read and write addresses is possible. table 1.11.2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k coefficient j coefficient k internal rom/ram no wait 1 1 internal rom/ram with wait 2 2 sfr area 2 2 separate bus no wait 1 2 separate bus one wait 2 2 separate bus two wait 3 3 separate bus three wait 4 4 multiplex bus 3 3 internal memory external memory dma request bit the dmac can issue dma requests using preselected dma request factors for each channel as trig- gers. the dma transfer request factors include the reception of dma request signals from the internal periph- eral functions, software dma factors generated by the program, and external factors using input from external interrupt signals. see the description of the dmai factor selection register for details of how to select dma request factors. dma requests are received as dma requests when the dmai request bit is set to 1 and the channel i transfer mode select bits are 01 or 11. therefore, even if the dmai request bit is 1, no dma request is received if the channel i transfer mode select bit is 00. in this case, dmai request bit is cleared. because the channel i transfer mode select bits default to 00 after a reset, remember to set the channel i transfer mode select bit for the channel to be activated after setting the dmac related registers. this enables receipt of the dma requests for that channel, and dma transfers are then performed when the dmai request bit is set. the following describes when the dmai request bit is set and cleared. memory expansion mode microprocessor mode single-chip mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 86 figure 1.11.7. dma transfer example by external factors bclk aaaa aaaa dma0 aaaaa aaaaa dma1 dma0 request bit dma1 request bit aaa aaaaaa a a a aaaaaa aa aa cpu int0 int1 in this example, dma transfer request signals are input simultaneously from external factors and the dma transfers are executed in the minimum cycles. bus priviledge acquired (1) internal factors the dmai request flag is set to 1 in response to internal factors at the same time as the interrupt request bit of the interrupt control register for each factor is set. this is because, except for software trigger dma factors, they use the interrupt request signals output by each function. the dmai request bit is cleared to "0" when the dma transfer starts or the dma transfer is in disable state (channel i transfer mode select bits are "00" and the dmai transfer count register is "0"). (2) external factors ______ these are dma request factors that are generated by the input edge from the inti pin (where i indi- ______ cates the dmac channel). when the inti pin is selected by the dmai request factor select bit as an external factor, the inputs from these pins become the dma request signals. when an external factor is selected, the dmai request bit is set, according to the function specified in the ______ dma request factor select bit, on either the falling edge of the signal input via the inti pins, or both edges. when an external factor is selected, the dmai request bit is cleared, in the same way as the dmai request bit is cleared for internal factors, when the dma transfer starts or the dma transfer is in disable state. (3) relationship between external factor request input and dmai request flag, and dma transfer timing when the request inputs to dmai occur in the same sampling cycle (between the falling edge of bclk and the next falling edge), the dmai request bits are set simultaneously, but if the dmai enable bits are all set, dma0 takes priority and the transfer starts. when one transfer unit is complete, the bus privilege is returned to the cpu. when the cpu has completed one bus access, dma1 transfer starts, and, when one transfer unit is complete, the privilege is again returned to the cpu. the priority is as follows: dma0 > dma1 > dma2 > dma3. figure 1.11.7. dma transfer example by external factors shows what happens when dma0 and dma1 requests occur in the same sampling cycle.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dmac 87 precautions for dmac (1) do not clear the dma request bit of the dmai request cause select register. in m16c/80, when a dma request is generated while the channel is disabled (note), the dma transfer is not executed and the dma request bit is cleared automatically. note :the dma is disabled or the transfer count register is "0". (2) when dma transfer is done by a software trigger, set dsr and drq of the dmai request cause select register to "1" simultaneously using the or instruction. e.g.) or.b #0a0h, dmisl ; dmisl is dmai request cause select register (3) when changing the dmai request cause select bit of the dmai request cause select register, set "1" to the dma request bit, simultaneously. in this case, the corresponding dma channel is set to disabled. at least 2 instructions are needed from the instruction to write to the dmai request cause select bit to enable dma. example) when dma request cause is changed to timer a0 and using dma0 in single transfer after dma initial setting push.w r0 ; store r0 register stc dmd0, r0 ; read dma mode register 0 and.b #11111100b, r0l ; clear dma0 transfer mode select bit to "00" ldc r0, dmd0 ; dma0 disabled mov.b #10000011b, dm0sl ; select timer a0 ; (write "1" to dma request bit simultaneously) mov.b r0l, r0l ; dummy cycle or.b #00000001b, r0l ; set dma0 single transfer ldc r0, dmd0 ; dma0 enabled pop.w r0 ; restore r0 register at least 2 instructions are needed until dma enabled.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 88 timer there are eleven 16-bit timers. these timers can be classified by function into timers a (five) and timers b (six). all these timers function independently. figures 1.12.1 and 1.12.2 show the block diagram of timers. ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ta0 in ta1 in ta2 in ta3 in ta4 in timer a0 timer a1 timer a2 timer a3 timer a4 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0341 16 ) set to ? reset clock prescaler timer b2 overflow figure 1.12.1. timer a block diagram
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 89 figure 1.12.2. timer b block diagram ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode tb0 in tb1 in tb2 in timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer b0 interrupt noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0341 16 ) set to ? reset clock prescaler timer b2 overflow (to timer a count source) ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode tb3 in tb4 in tb5 in timer b3 timer b4 timer b5 timer b3 interrupt noise filter noise filter noise filter timer b1 interrupt timer b2 interrupt timer b4 interrupt timer b5 interrupt
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 90 timer a figure 1.13.1 shows the block diagram of timer a. figures 1.13.2 to 1.13.4 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure 1.13.2. timer a-related registers (1) count start flag (address 0340 16 ) up count/down count tai addresses taj tak timer a0 0347 16 0346 16 timer a4 timer a1 timer a1 0349 16 0348 16 timer a0 timer a2 timer a2 034b 16 034a 16 timer a1 timer a3 timer a3 034d 16 034c 16 timer a2 timer a4 timer a4 034f 16 034e 16 timer a3 timer a0 always down count except in event counter mode reload register (16) counter (16) low-order 8 bits aaaa aaaa high-order 8 bits clock source selection timer (gate function) timer one shot pwm f 1 f 8 f 32 external trigger tai in (i = 0 to 4) tb2 overflow event counter f c32 clock selection taj overflow (j = i e 1. note, however, that j = 4 when i = 0) pulse output toggle flip-flop tai out (i = 0 to 4) data bus low-order bits data bus high-order bits a a a up/down flag down count (address 0344 16 ) tak overflow (k = i + 1. note, however, that k = 0 when i = 4) polarity selection timer ai mode register symbol address when reset taimr(i=0 to 4) 0356 16 to 035a 16 00000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit a aa a aa a a aa aa a aa a a aa aa a aa a a aa aa a aa this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. figure 1.13.1. block diagram of timer a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 91 figure 1.13.3. timer a-related registers (2) timer a4 up/down flag timer a3 up/down flag timer a2 up/down flag timer a1 up/down flag timer a0 up/down flag timer a2 two-phase pulse signal processing select bit timer a3 two-phase pulse signal processing select bit timer a4 two-phase pulse signal processing select bit symbol address when reset udf 0344 16 00 16 ta4p ta3p ta2p up/down flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ta4ud ta3ud ta2ud ta1ud ta0ud 0 : down count 1 : up count this specification becomes valid when the up/down flag content is selected for up/down switching cause 0 : two-phase pulse signal processing disabled 1 : two-phase pulse signal processing enabled when not using the two-phase pulse signal processing function, set the select bit to ? symbol address when reset tabsr 0340 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s symbol address when reset ta0 0347 16 ,0346 16 indeterminate ta1 0349 16 ,0348 16 indeterminate ta2 034b 16 ,034a 16 indeterminate ta3 034d 16 ,034c 16 indeterminate ta4 034f 16 ,034e 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer ai register (note) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set event counter mode 0000 16 to ffff 16 counts pulses from an external source or timer overflow one-shot timer mode 0000 16 to ffff 16 counts a one shot width pulse width modulation mode (16-bit pwm) functions as a 16-bit pulse width modulator pulse width modulation mode (8-bit pwm) timer low-order address functions as an 8-bit prescaler and high-order address functions as an 8-bit pulse width modulator 00 16 to fe 16 (both high-order and low-order addresses) 0000 16 to fffe 16 note: read and write data in 16-bit units. aa a aa a aa a aa aa a a aa a aa a aa aa a a aa a aa aa a a aa a aa a aa a aa a a a a a aa a aa a a a a a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 92 symbol address when reset cpsrf 0341 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr w r nothing is assigned. when write, set "0". when read, their contents are indeterminate. ta1tgl symbol address when reset trgsr 0343 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 ta1os ta2os ta0os one-shot start flag symbol address when reset onsf 0342 16 00 16 timer a0 one-shot start flag timer a1 one-shot start flag timer a2 one-shot start flag timer a3 one-shot start flag timer a4 one-shot start flag ta3os ta4os bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 ta0tgl ta0tgh 0 0 : input on ta0 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta4 overflow is selected 1 1 : ta1 overflow is selected timer a0 event/trigger select bit b7 b6 note: set the corresponding pin output function select register to i/o port, and port direction register to 0. w r 1 : timer start when read, the value is 0 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a z phase input enable bit tazie 0 : invalid 1 : valid note: set the corresponding port function select register to i/o port, and port direction register to 0. figure 1.13.4. timer a-related registers (3)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 93 item specification count source f 1 , f 8 , f 32 , fc 32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output (setting by corresponding port function select register and peripheral function select register) read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.13.1.) figure 1.13.5 shows the timer ai mode register in timer mode. table 1.13.1. specifications of timer mode note 1: the bit can be ??or ?? note 2: set the corresponding port function select register to i/o port, and port direction register to ?? timer ai mode register symbol address when reset taimr(i=0 to 4) 0356 16 to 035a 16 00000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 gate function select bit 0 x (note 2) : gate function not available (tai in pin is a normal port pin) 1 0 : timer counts only when ta iin pin is held ??(note 2) 1 1 : timer counts only when ta iin pin is held ??(note 2) b4 b3 mr2 mr1 mr3 0 (must always be fixed to ??in timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 00 0 a aa a a aa aa a a aa aa a aa a a aa aa a a aa aa a a aa aa a aa this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. figure 1.13.5. timer ai mode register in timer mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 94 item specification count source ? external signals input to tai in pin (effective edge can be selected by software) ? tb2 overflows or underflows , taj overflows or underflows count operation ? up count or down count can be selected by external signal or software ? when the timer overflows or underflows, it reloads the reload register con tents before continuing counting (note) divide ratio ? 1/ (ffff 16 - n + 1) for up count ? 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input (setting by corresponding port function select register and peripheral function select register) read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ? pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single- phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table 1.13.2 lists timer specifications when counting a single-phase external signal. figure 1.13.6 shows the timer ai mode register in event counter mode. table 1.13.3 lists timer specifications when counting a two-phase external signal. figure 1.13.7 shows the timer ai mode register in event counter mode. table 1.13.2. timer specifications in event counter mode (when not processing two-phase pulse signal) figure 1.13.6. timer ai mode register in event counter mode timer ai mode register w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode (note 1) b1 b0 tmod0 mr0 count polarity select bit (note 2) mr2 mr1 mr3 0 (must always be fixed to ??in event counter mode) tck0 count operation type select bit 01 0 0 : counts external signal's falling edge 1 : counts external signal's rising edge up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 3) 0 : reload type 1 : free-run type bit symbol bit name function rw tck1 invalid in event counter mode can be ??or ? tmod1 a aa a a aa aa a aa a a aa aa a aa a aa a aa a aa note 1: in event counter mode, the count source is selected by the event / trigger select bit (addresses 0342 16 and 0343 16 ). note 2: valid only when counting an external signal. note 3: when an l signal is input to the tai out pin, the downcount is activated. when h, the upcount is activated. set the corresponding port function select register to i/o port, and port direction register to 0. symbol address when reset taimr(i=0 to 4) 0356 16 to 035a 16 00000x00 2 this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. note: this does not apply when the free-run function is selected.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 95 item specification count source ? two-phase pulse signals input to tai in or tai out pin count operation ? up count or down count can be selected by two-phase pulse signal ? when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio ? 1/ (ffff 16 - n + 1) for up count ? 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input (setting by corresponding port function select register and peripheral function select register) read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ? when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ? when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function ? normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ? multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. table 1.13.3. timer specifications in event counter mode tai out up count up count up count down count down count down count tai in (i=2,3) tai out tai in (i=3,4) count up all edges count up all edges count down all edges count down all edges (when processing two-phase pulse signal with timers a2, a3, and a4) note: this does not apply when the free-run function is selected.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 96 note 1: this bit is valid when only counting an external signal. note 2: set the corresponding function select register a to i/o port, and port direction register to ?? note 3: this bit is valid for the timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ? ?r ?? note 4: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0344 16 ) is set to ?? also, always be set the event/trigger select bit (address 0343 16 ) to ?0? timer ai mode register (when not using two-phase pulse signal processing) b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 0 : (must always be ??in event counter mode) tck1 tck0 01 0 0 : counts external signal's falling edges 1 : counts external signal's rising edges up/down switching cause select bit 0 : up/down flag's content 1 : ta iout pin's input signal (note 2) bit symbol bit name function w r count operation type select bit two-phase pulse signal processing operation select bit (note 3,4) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation note 1: set the corresponding function select register a to i/o port. note 2: this bit is valid for timer a3 mode register. for timer a2 and a4 mode registers, this bit can be ??or ?? note 3: when performing two-phase pulse signal processing, make sure the two-phase pulse signal processing operation select bit (address 0344 16 ) is set to ?? also, always be sure to set the event/trigger select bit (addresses 0342 16 and 0343 16 ) to ?0? timer ai mode register (when using two-phase pulse signal processing) symbol address when reset taimr(i=2 to 4) 0358 16 to 035a 16 00000x00 2 b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 0 (must always be ??when using two-phase pulse signal processing) mr2 mr1 mr3 0 (must always be ??when using two-phase pulse signal processing) tck1 tck0 01 0 1 (must always be ??when using two-phase pulse signal processing) bit symbol bit name function w r count operation type select bit two-phase pulse processing operation select bit (note 2)(note 3) 0 : reload type 1 : free-run type 0 : normal processing operation 1 : multiply-by-4 processing operation 0 0 1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a symbol address when reset taimr(i=2 to 4) 0358 16 to 035a 16 00000x00 2 this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. (note 1) figure 1.13.7. timer ai mode register in event counter mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 97 ? counter resetting by two-phase pulse signal processing this function resets the timer counter to 0 when the z-phase (counter reset) is input during two- phase pulse signal processing. this function can only be used in timer a3 event counter mode, two-phase pulse signal processing, free-run type, and multiply-by-4 processing. the z phase is input to the int2 pin. when the z-phase input enable bit (bit 5 at address 0342 16 ) is set to 1, the counter can be reset by z-phase input. for the counter to be reset to 0 by z-phase input, you must first write 0000 16 to the timer a3 register (address 034d 16 and 034c 16 ). the z-phase is input when the int2 input edge is detected. the edge polarity is selected by the int2 polarity switch bit (bit 5 at address 009c 16 ). the z-phase must have a pulse width greater than 1 cycle of the timer a3 count source. figure 1.13.8 shows the relationship between the two-phase pulse (a phase and b phase) and the z phase. the counter is reset at the count source following z-phase input. figure 1.13.9 shows the timing at which the counter is reset to 0. the pulse must be wider than this width. note: select rising edge. ta3 out (a phase) count source ta3 in (b phase) int2 (z phase) figure 1.13.8. the relationship between the two-phase pulse (a phase and b phase) and the z phase
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 98 figure 1.13.9. the counter reset timing note that two timer a3 interrupt requests occur successively two times when timer a3 underflow and int2 input reload are happened at the same timing. do not use timer a3 interrupt request when this function is used. ta3 out (a phase) count source ta3 in (b phase) becoming "0" at this timing. count value mm+1 1 2 3 4 5 int2 (z phase) (note) note: select rising edge.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 99 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output (setting by corresponding port function select register and peripheral function select register) read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) table 1.13.4. timer specifications in one-shot timer mode figure 1.13.10. timer ai mode register in one-shot timer mode (3) one-shot timer mode in this mode, the timer operates only once. (see table 1.13.4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure 1.13.10 shows the timer ai mode register in one-shot timer mode. bit name timer ai mode register function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 0 : one-shot start flag is valid 1 : selected by event/trigger select register trigger select bit external trigger select bit (note 1) 0 : falling edge of tai in pin's input signal (note 2) 1 : rising edge of tai in pin's input signal (note 2) note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 and 0343 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port function select register to i/o port, and port direction re g ister to ?? w r a a aa aa a aa a aa a aa a aa a aa a aa a aa symbol address when reset taimr(i=0 to 4) 0356 16 to 035a 16 00000x00 2 this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 100 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ? the timer is not affected by a trigger that occurs when counting 16-bit pwm ? high level width n / fi n : set value ? cycle time (2 16 -1) / fi fixed 8-bit pwm ? high level width n (m+1) / fi n : values set to timer ai registers high-order address ? cycle time (2 8 -1) (m+1) / fi m:values set to timer ai registers low-order address count start condition ? external trigger is input ? the timer overflows ? the count start flag is set (= 1) count stop condition ? the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output two-phase pulse input (setting by corresponding port function select register and peripheral function select register) read from timer when timer ai register is read, it indicates an indeterminate value write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table 1.13.5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure 1.13.11 shows the timer ai mode register in pulse width modulation mode. figure 1.13.12 shows the example of how a 16-bit pulse width modulator operates. figure 1.13.13 shows the example of how an 8-bit pulse width modulator operates. figure 1.13.11. timer ai mode register in pulse width modulation mode table 1.13.5. timer specifications in pulse width modulation mode bit name timer ai mode register function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 1 : pwm mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit w r 11 1 16/8-bit pwm mode select bit 0: functions as a 16-bit pulse width modulator 1: functions as an 8-bit pulse width modulator trigger select bit external trigger select bit (note 1) 0: falling edge of tai in pin's input signal (note 2) 1: rising edge of tai in pin's input signal (note 2) 0: count start flag is valid 1: selected by event/trigger select register note 1: valid only when the ta iin pin is selected by the event/trigger select bit (addresses 0342 16 and 0343 16 ). if timer overflow is selected, this bit can be ??or ?? note 2: set the corresponding port function select register to i/o port, and port direction register to ?? a a aa aa a aa a a aa aa a aa a aa a aa a a aa aa a aa symbol address when reset taimr(i=0 to 4) 0356 16 to 035a 16 00000x00 2 this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer a 101 1 / f i x (2 ?1) 16 count source ta iin pin input signal pwm pulse output from ta iout pin condition : reload register = 0003 16 , when external trigger (rising edge of ta iin pin input signal) is selected trigger is not generated by this signal ? ? ? ? timer ai interrupt request bit ? ? cleared to ??when interrupt request is accepted, or cleared by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note: n = 0000 16 to fffe 16 . 1 / f i x n count source (note1) ta iin pin input signal underflow signal of 8-bit prescaler (note2) pwm pulse output from ta iout pin ? ? ? ? ? ? ? ? timer ai interrupt request bit cleared to ??when interrupt request is accepted, or cleaerd by software f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) note 1: the 8-bit prescaler counts the count source. note 2: the 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal. note 3: m = 00 16 to fe 16 ; n = 00 16 to fe 16 . aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa condition : reload register high-order 8 bits = 02 16 reload register low-order 8 bits = 02 16 external trigger (falling edge of ta iin pin input signal) is selected 1 / f i x (m + 1) x (2 e 1) 8 1 / f i x (m + 1) x n 1 / f i x (m + 1) figure 1.13.12. example of how a 16-bit pulse width modulator operates figure 1.13.13. example of how an 8-bit pulse width modulator operates
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 102 timer b figure 1.14.1 shows the block diagram of timer b. figures 1.14.2 and 1.14.3 show the timer b-related registers. use the timer bi mode register (i = 0 to 5) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure 1.14.1. block diagram of timer b timer bi mode register symbol address when reset tbimr(i = 0 to 5) 035b 16 to 035d 16 00xx0000 2 031b 16 to 031d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : pulse period/pulse width measurement mode 1 1 : inhibited b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit (note 1) (note 2) note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. aa aa a a aa a aa a aa aa a a aa a aa aa a a aa a aa clock source selection (address 0340 16 ) event counter timer pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i e 1. note, however, j = 2 when i = 0, j = 5 when i = 3) can be selected in only event counter mode count start flag f c32 polarity switching and edge pulse tbi in (i = 0 to 5) counter reset circuit counter (16) tbi address tbj timer b0 0351 16 0350 16 timer b2 timer b1 0353 16 0352 16 timer b0 timer b2 0355 16 0354 16 timer b1 timer b3 0311 16 0310 16 timer b5 timer b4 0313 16 0312 16 timer b3 timer b5 0315 16 0314 16 timer b4 figure 1.14.2. timer b-related registers (1)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 103 symbol address when reset tabsr 0340 16 00 16 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s function a aa a a aa aa a aa a aa a aa a a aa aa a aa a aa symbol address when reset cpsrf 0381 16 0xxxxxxx 2 clock prescaler reset flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa clock prescaler reset flag 0 : no effect 1 : prescaler is reset (when read, the value is 0) cpsr a a aa aa symbol address when reset tb0 0351 16 , 0350 16 indeterminate tb1 0353 16 , 0352 16 indeterminate tb2 0355 16 , 0354 16 indeterminate tb3 0311 16 , 0310 16 indeterminate tb4 0313 16 , 0312 16 indeterminate tb5 0315 16 , 0314 16 indeterminate b7 b0 b7 b0 (b15) (b8) timer bi register (note) w r pulse period / pulse width measurement mode measures a pulse period or width timer mode 0000 16 to ffff 16 counts the timer's period function values that can be set event counter mode 0000 16 to ffff 16 counts external pulses input or a timer overflow note: read and write data in 16-bit units. a aa a a aa aa a symbol address when reset tbsr 0300 16 000xxxxx 2 timer b3, 4, 5 count start flag bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa aaaaaaaaaaaaaaa timer b5 count start flag timer b4 count start flag timer b3 count start flag 0 : stops counting 1 : starts counting tb5s tb4s tb3s nothing is assigned. when write, set "0". when read, the value of these bits is indeterminate. function a aa a a aa aa a aa nothing is assigned. when write, set "0". when read, the value of these bits is indeterminate. figure 1.14.3. timer b-related registers (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 104 item specification count source f1, f8, f32, fc32 count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbiin pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table 1.14.1.) figure 1.14.4 shows the timer bi mode register in timer mode. table 1.14.1. timer specifications in timer mode note 1: timer b0, timer b3. note 2: timer b1, timer b2, timer b4, timer b5. timer bi mode register symbol address when reset tbimr(i = 0 to 5) 035b 16 to 035d 16 00xx0000 2 031b 16 to 031d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa a a operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. when write, set "0". when read in timer mode, its content is indeterminate. 0 0 (fixed to 0 in timer mode ; i = 0, 3) nothing is assiigned (i = 1, 2, 4, 5). when write, set "0". when read, its content is indeterminate. (note 1) (note 2) b7 b6 a aa a aa a a aa aa a aa a aa a aa a aa a a figure 1.14.4. timer bi mode register in timer mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 105 item specification count source ? external signals input to tbiin pin effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software ? tbj overflows or underflows count operation ? counts down ? when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbiin pin function count source input (set the corresponding function select register a to i/o port.) read from timer count value can be read out by reading timer bi register write to timer ? when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table 1.14.2.) figure 1.14.5 shows the timer bi mode register in event counter mode. table 1.14.2 . timer specifications in event counter mode figure 1.14.5. timer bi mode register in event counter mode timer bi mode register symbol address when reset tbimr(i = 0 to 5) 035b 16 to 035d 16 00xx0000 2 031b 16 to 031d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aa aa operation mode select bit 0 1 : event counter mode b1 b0 tmod1 tmod0 mr0 count polarity select bit (note 1) mr2 mr1 mr3 invalid in event counter mode. when write, set "0". when read in event counter mode, its content is indeterminate. tck1 tck0 01 0 0 : counts external signal's falling edges 0 1 : counts external signal's rising edges 1 0 : counts external signal's falling and rising edges 1 1 : inhibited b3 b2 nothing is assigned (i = 1, 2, 4, 5). when write, set "0". when read, its content is indeterminate. note 1: valid only when input from the tbi in pin is selected as the event clock. if timer's overflow is selected, this bit can be 0 or 1. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. note 4: set the corresponding function select register a to i/o port, and port direction register to 0. invalid in event counter mode. can be 0 or 1. event clock select 0 : input from tbi in pin (note 4) 1 : tbj overflow (j = i e 1; however, j = 2 when i = 0, j = 5 when i = 3) 0 (fixed to 0 in event counter mode; i = 0, 3) (note 2) (note 3) aa a aa aa a a aa aa a a aa a aa a aa a aa a aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 106 item specification count source f1, f8, f32, fc32 count operation ? up count ? counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ? when measurement pulse's effective edge is input (note 1) ? when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbiin pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table 1.14.3.) figure 1.14.6 shows the timer bi mode register in pulse period/pulse width measurement mode. figure 1.14.7 shows the operation timing when measuring a pulse period. figure 1.14.8 shows the operation timing when measuring a pulse width. table 1.14.3. timer specifications in pulse period/pulse width measurement mode figure 1.14.6. timer bi mode register in pulse period/pulse width measurement mode note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the time r. timer bi mode register symbol address when reset tbimr(i = 0 to 5) 035b 16 to 035d 16 00xx0000 2 031b 16 to 031d 16 00xx0000 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : pulse period / pulse width measurement mode b1 b0 tmod1 tmod0 mr0 measurement mode select bit mr2 mr1 mr3 tck1 tck0 0 1 0 0 : pulse period measurement (interval between measurement pulse's falling edge to falling edge) 0 1 : pulse period measurement (interval between measurement pulse's rising edge to rising edge) 1 0 : pulse width measurement (interval between measurement pulse's falling edge to rising edge, and between rising edge to falling edge) 1 1 : inhibited function b3 b2 nothing is assigned (i = 1, 2, 4, 5). when write, set "0". when read, its content is indeterminate. count source select bit timer bi overflow flag ( note 1) 0 : timer did not overflow 1 : timer has overflowed 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 note 1: the timer bi overflow flag changes to ??when the count start flag is ??and a value is written to the timer bi mode register. this flag cannot be set to ??by software. note 2: timer b0, timer b3. note 3: timer b1, timer b2, timer b4, timer b5. 0 (fixed to ??in pulse period/pulse width measurement mode; i = 0, 3) (note 2) (note 3) aa a aa aa a a aa a aa a aa a aa a aa a aa aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timer b 107 figure 1.14.8. operation timing when measuring a pulse width measurement pulse ? count source count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (measured value) transfer (measured value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) transfer (measured value) (note 1) cleared to ??when interrupt request is accepted, or cleared by software. (note 2) transfer (indeterminate value) reload register counter transfer timing figure 1.14.7. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing at which counter reaches ?000 16 ? ? transfer (indeterminate value) ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) when measuring measurement pulse time interval from falling edge to falling edge (note 2) cleared to ??when interrupt request is accepted, or cleared by software. transfer (measured value) ? reload register counter transfer timing
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 108 three-phase motor control timers functions use of more than one built-in timer a and timer b provides the means of outputting three-phase motor driving waveforms. figures 1.15.1 through 1.15.3 show registers related to timers for three-phase motor control. no value other than ??can be written. selecting three-phase pwm output mode causes the dead time timer, the u, v, w phase output control circuits, and the timer b2 interrupt frequency set circuit works. for u, u, v, v, w and w output from p8 0 , p8 1 , and p7 2 through p7 5 , setting of port function select register, peripheral function select register and peripheral subfunction select regoster are required. in triangular wave modulation mode: the dead time timer starts in synchronization with the falling edge of timer ai output. the data transfer from the three-phase buffer register to the three-phase output shift register is made only once in synchronization with the transfer trigger signal after writing to the three-phase output buffer register. in sawtooth wave modulation mode: the dead time timer starts in synchronization with the falling edge of timer a output and with the transfer trigger signal. the data transfer from the three-phase output buffer register to the three- phase output shift register is made with respect to every transfer trigger. set bit 1 of this register to "1" after setting timer b2 interrupt frequency set counter. three-phase pwm control register 0 symbol address when reset invc0 0308 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 effective interrupt output polarity select bit inv0 0 bit symbol bit name description rw inv0 1 effective interrupt output specification bit inv0 2 mode select bit (note 2) inv0 4 positive and negative phases concurrent l output disable function enable bit inv0 7 software trigger bit inv0 6 modulation mode select bit (note 3) inv0 5 positive and negative phases concurrent l output detect flag inv0 3 output control bit 0: a timer b2 interrupt occurs when the timer a1 reload control signal is ?? 1: a timer b2 interrupt occurs when the timer a1 reload control signal is ?? effective only in three-phase mode 1 0: not specified. 1: selected by the effective interrupt output polarity selection bit. effective only in three-phase mode 1 0: normal mode 1: three-phase pwm output mode 0: output disabled 1: output enabled 0: feature disabled 1: feature enabled 0: not detected yet 1: already detected 0: triangular wave modulation mode 1: sawtooth wave modulation mode 1: trigger generated the value, when read, is ?? (note 1) t hree-phase pwm control register 1 symbol address when reset invc1 0309 16 xxx0x000 2 bit name description bit symbol w r inv1 0 inv1 1 inv1 2 timer ai start trigger signal select bit timer a1-1, a2-1, a4-1 control bit dead time timer count source select bit 0: timer b2 overflow signal 1: timer b2 overflow signal, signal for writing to timer b2 0: three-phase mode 0 1: three-phase mode 1 0 : inhibit 1 : f 1 /2 (note) b7 b6 b5 b4 b3 b2 b1 b0 noting is assigned. when write, set "0". when read, their contents are "0". note 1: note 2: note 3: note 4: note : inv1 2 is valid when inv0 6 = 0 and inv1 1 = 1. inv1 3 inv1 4 carrier wave detect flag output porality control bit 0: rising edge of triangular waveform 1: falling edge of triangular waveform 0 : low active 1 : high active figure 1.15.1. registers related to timers for three-phase motor control
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 109 three-phase output buffer register 0 (note) symbol address when reset idb0 030a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set "0". when read, its content is "0". du0 dub0 dv0 dw0 dvb0 dwb0 u phase output buffer 0 setting in u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 u phase output buffer 0 v phase output buffer 0 w phase output buffer 0 setting in v phase output buffer 0 setting in w phase output buffer 0 setting in w phase output buffer 0 setting in v phase output buffer 0 setting in u phase output buffer 0 three-phase output buffer register 1 (note) symbol address when reset idb1 030b 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 nothing is assigned. when write, set "0". when read, its content is "0". du1 dub1 dv1 dw1 dvb1 dwb1 u phase output buffer 1 setting in u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 u phase output buffer 1 v phase output buffer 1 w phase output buffer 1 setting in v phase output buffer 1 setting in w phase output buffer 1 setting in w phase output buffer 1 setting in v phase output buffer 1 setting in u phase output buffer 1 dead time timer symbol address when reset dot 030c 16 indeterminate function values that can be set w r b7 b0 set dead time timer 1 to 255 timer b2 interrupt occurrences frequency set counter symbol address when reset ictb2 030d 16 indeterminate function values that can be set w r b3 b0 set occurrence frequency of timer b2 interrupt request 1 to 15 note: when executing read instruction of this register, the contents of three-phase shift register is read out. note: when executing read instruction of this register, the contents of three-phase shift register is read out. note 1: when the effective interrupt output specification bit (inv01: bit 1 at 0308 16 ) is set to "1" and three-phase motor control timer is operating, do not rewrite to this register. note 2: do not write to this register at the timing of timer b2 overflow. figure 1.15.2. registers related to timers for three-phase motor control
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 110 figure 1.15.3. registers related to timers for three-phase motor control symbol address when reset ta11 0303 16 ,0302 16 indeterminate ta21 0305 16 ,0304 16 indeterminate ta41 0307 16 ,0306 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r counts an internal count source 0000 16 to ffff 16 function values that can be set timer ai-1 register (note) note: read and write data in 16-bit units. a a symbol address when reset ta1 0349 16 ,0348 16 indeterminate ta2 034b 16 ,034a 16 indeterminate ta4 034f 16 ,034e 16 indeterminate tb2 0355 16 ,0354 16 indeterminate b7 b0 b7 b0 (b15) (b8) w r timer mode 0000 16 to ffff 16 counts an internal count source function values that can be set one-shot timer mode 0000 16 to ffff 16 counts a one shot width note: read and write data in 16-bit units. timer ai register (note) a a a a a ta1tgl symbol address when reset trgsr 0343 16 00 16 timer a1 event/trigger select bit 0 0 : input on ta1 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta0 overflow is selected 1 1 : ta2 overflow is selected trigger select register bit name function bit symbol b0 0 0 : input on ta2 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta1 overflow is selected 1 1 : ta3 overflow is selected 0 0 : input on ta3 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta2 overflow is selected 1 1 : ta4 overflow is selected 0 0 : input on ta4 in is selected (note) 0 1 : tb2 overflow is selected 1 0 : ta3 overflow is selected 1 1 : ta0 overflow is selected timer a2 event/trigger select bit timer a3 event/trigger select bit timer a4 event/trigger select bit w r ta1tgh ta2tgl ta2tgh ta3tgl ta3tgh ta4tgl ta4tgh b1 b0 b3 b2 b5 b4 b7 b6 note: set the corresponding port function select register to i/o port, and port direction register to "0". a aa a aa a aa a aa a a aa aa a a aa aa a a aa aa a aa a aa b7 b6 b5 b4 b3 b2 b1 symbol address when reset tabsr 0340 16 00 16 count start flag bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa aaaaaaaaaaaaaa timer b2 count start flag timer b1 count start flag timer b0 count start flag timer a4 count start flag timer a3 count start flag timer a2 count start flag timer a1 count start flag timer a0 count start flag 0 : stops counting 1 : starts counting tb2s tb1s tb0s ta4s ta3s ta2s ta1s ta0s aa aa a a aa a aa aa a a aa a aa a aa aa a a aa a aa a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 111 bit name timer ai mode register symbol address when reset ta1mr 0357 16 00000x00 2 ta2mr 0358 16 00000x00 2 ta3mr 035a 16 00000x00 2 function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 operation mode select bit 1 0 : one-shot timer mode b1 b0 tmod1 tmod0 mr0 mr2 mr1 mr3 0 (must always be ??in one-shot timer mode) 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 b7 b6 tck1 tck0 count source select bit 10 0 1 : selected by event/trigger select register trigger select bit external trigger select bit invalid in three-phase pwm waveform mode. w r a a a a a a a a a a a a a a a a a a timer b2 mode register symbol address when reset tb2mr 035d 16 00xx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa operation mode select bit 0 0 : timer mode b1 b0 tmod1 tmod0 mr0 invalid in timer mode can be 0 or 1 mr2 mr1 mr3 0 0 : f 1 0 1 : f 8 1 0 : f 32 1 1 : f c32 tck1 tck0 count source select bit 0 invalid in timer mode. when write, set "0". when read in timer mode, its content is indeterminate. 0 0 (fixed to 0 in timer mode) b7 b6 a a a a a a a a a a a a a a a a a a a 1 0 this bit is invalid in m16c/80 series. port output control is set by the function select registers a and b. figure 1.15.4. timer mode registers in three-phase waveform mode three-phase motor driving waveform output mode (three-phase waveform mode) setting 1 in the mode select bit (bit 2 at 0308 16 ) shown in figure 1.15.1 - causes three-phase waveform mode that uses four timers a1, a2, a4, and b2 to be selected. as shown in figure 1.15.4, set timers a1, a2, and a4 in one-shot timer mode, set the trigger in timer b2, and set timer b2 in timer mode using the respective timer mode registers.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 112 figure 1.15.5 shows the block diagram for three-phase waveform mode. in l active output polarity in three-phase waveform mode, the positive-phase waveforms (u phase, v phase, and w phase) and ___ ___ ___ negative waveforms (u phase, v phase, and w phase), six waveforms in total, are output from p8 1 , p7 2 , p7 3 , p7 4 , and p7 5 as active on the l level. of the timers used in this mode, timer a4 controls the u ___ ___ phase and u phase, timer a1 controls the v phase and v phase, and timer a2 controls the w phase and ___ w phase respectively; timer b2 controls the periods of one-shot pulse output from timers a4, a1, and a2. in outputting a waveform, dead time can be set so as to cause the l level of the positive waveform ___ output (u phase, v phase, and w phase) not to lap over the l level of the negative waveform output (u ___ ___ phase, v phase, and w phase). to set short circuit time, use three 8-bit timers sharing the reload register for setting dead time. a value from 1 through 255 can be set as the count of the timer for setting dead time. the timer for setting dead time works as a one-shot timer. if a value is written to the dead timer (030c 16 ), the value is written to the reload register shared by the three timers for setting dead time. any of the timers for setting dead time takes the value of the reload register into its counter, if a start trigger comes from its corresponding timer, and performs a down count in line with the clock source selected by the dead time timer count source select bit (bit 2 at 0309 16 ). the timer can receive another trigger again before the workings due to the previous trigger are completed. in this instance, the timer performs a down count from the reload registers content after its transfer, provoked by the trigger, to the timer for setting dead time. since the timer for setting dead time works as a one-shot timer, it starts outputting pulses if a trigger comes; it stops outputting pulses as soon as its content becomes 00 16 , and waits for the next trigger to come. ___ ___ the positive waveforms (u phase, v phase, and w phase) and the negative waveforms (u phase, v ___ phase, and w phase) in three-phase waveform mode are output from respective ports by means of setting 1 in the output control bit (bit 3 at 0308 16 ). setting 0 in this bit causes the ports to be the high- impedance state. this bit can be set to 0 not only by use of the applicable instruction, but by entering a _______ falling edge in the nmi terminal or by resetting. also, if 1 is set in the positive and negative phases ___ concurrent l output disable function enable bit (bit 4 at 0308 16 ) causes one of the pairs of u phase and u ___ ___ phase, v phase and v phase, and w phase and w phase concurrently go to l, as a result, the output control bit becomes the high-impedance state.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 113 timer b2 (timer mode) overflow interrupt occurrence frequency set counter interrupt request bit u(p8 0 ) u(p8 1 ) v(p7 2 ) v(p7 3 ) w(p7 4 ) w(p7 5 ) nmi reset r d d t q d t q d t q d t q for short circuit prevention d t q d t q q inv0 3 inv0 5 diagram for switching to p8 0 , p8 1 , and to p7 2 - p7 5 is not shown. inv0 4 timer a4 counter (one-shot timer mode) (one-shot timer mode) (one-shot timer mode) trigger timer a4 reload timer a4-1 timer a1 counter trigger timer a1 reload timer a1-1 timer a2 counter trigger timer a2 reload timer a2-1 inv0 7 t q inv1 1 dead time timer setting (8) inv0 0 1 0 inv0 1 inv1 1 du0 du1 t dq t dq dub0 dub1 t dq t dq u phase output control circuit u phase output signal u phase output signal v phase output control circuit to be set to ??when timer a4 stops t q inv1 1 to be set to ??when timer a1 stops t q inv1 1 to be set to ??when timer a2 stops u phase output control circuit v phase output signal w phase output signal v phase output signal w phase output signal signal to be written to b2 trigger signal for timer ai start trigger signal for transfer inv1 0 circuit foriinterrupt occurrence frequency set counter bit 0 at 030b 16 bit 0 at 030a 16 three-phase output shift register (u phase) control signal for timer a4 reload a f 1 inv1 2 0 1 1/2 n = 1 to 15 reload register n = 1 to 255 dead time timer setting n = 1 to 255 dead time timer setting (8) n = 1 to 255 n = 1 to 255 trigger inv0 6 trigger trigger trigger trigger trigger inv0 6 inv0 6 inv1 4 figure 1.15.5. block diagram for three-phase waveform mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 114 triangular wave modulation to generate a pwm waveform of triangular wave modulation, set 0 in the modulation mode select bit (bit 6 at 0308 16 ). also, set 1 in the timers a4-1, a1-1, a2-1 control bit (bit 1 at 0309 16 ). in this mode, each of timers a4, a1, and a2 has two timer registers, and alternately reloads the timer registers content to the counter every time timer b2 counters content becomes 0000 16 . if 1 is set to the effective interrupt output specification bit (bit 1 at 0308 16 ), the frequency of interrupt requests that occur every time the timer b2 counters value becomes 0000 16 can be set by use of the timer b2 counter (030d 16 ) for setting the frequency of interrupt occurrences. the frequency of occurrences is given by (setting; setting p 0). setting 1 in the effective interrupt output specification bit (bit 1 at 0308 16 ) provides the means to choose which value of the timer a1 reload control signal to use, 0 or 1, to cause timer b2s interrupt request to occur. to make this selection, use the effective interrupt output polarity selection bit (bit 0 at 0308 16 ). an example of u phase waveform is shown in figure 74, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 030a 16 ). and set 0 in dub0 (bit 1 at 030a 16 ). in addition, set 0 in du1 (bit 0 at 030b 16 ) and set 1 in dub1 (bit 1 at 030b 16 ). also, set 0 in the effective interrupt output specification bit (bit 1 at 0308 16 ) to set a value in the timer b2 interrupt occurrence frequency set counter. by this setting, a timer b2 interrupt occurs when the timer b2 counters content becomes 0000 16 as many as (setting) times. furthermore, set 1 in the effective interrupt output specification bit (bit 1 at 0308 16 ), set in the effective interrupt polarity select bit (bit 0 at 0308 16 ) and set "1" in the interrupt occurrence frequency set counter (030d 16 ). these settings cause a timer b2 interrupt to occur every other interval when the u phase output goes to h. when the timer b2 counters content becomes 0000 16 , timer a4 starts outputting one-shot pulses. in this instance, the content of du1 (bit 0 at 030b 16 ) and that of du0 (bit 0 at 030a 16 ) are set in the three-phase output shift register (u phase), the content of dub1 (bit 1 at 030b 16 ) and that of dub0 (bit 1 at 030a 16 ) ___ are set in the three-phase shift register (u phase). after triangular wave modulation mode is selected, however, no setting is made in the shift register even though the timer b2 counters content becomes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (038f 16 , 038e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase shift registers content is shifted one posi- ___ tion, and the value of du1 and that of dub1 are output to the u phase output signal and to u phase output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for ___ setting the time over which the l level of the u phase waveform doesnt lap over the l level of the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, "0" already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the "l" level. when the timer b2 counters content becomes 0000 16 , the timer a4 counter starts counting the value written to timer a4-1 (0307 16 , 0306 16 ), and starts outputting one-shot pulses. when timer a4 fin- ishes outputting one-shot pulses, the three-phase shift registers content is shifted one position, but if the three-phase output shift registers content changes from 0 to 1 as a result of the shift, the output level changes from l to h without waiting for the timer for setting dead time to finish outputting one-shot pulses. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 115 timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase a carrier wave of triangular waveform carrier wave signal wave u phase output signal control signal for timer a4 reload u phase u phase output signal mn nmpo note 1: when inv14="0" (output wave low active) note 2: when inv14="1" (output wave high active) note 3: set to trian g ular wave modulation mode and to three- p hase mode 1. m inv13(triangular wave modulation detect flag) (note 1) (note 2) (note 3) u phase u phase dead time dead time timber b2 interrupt occurres rewriting timer a4 and timer a4-1. possible to set the number of overflows to generate an interrupt by use of the interrupt occurrences frequency set circuit the three-phase shift register shifts in synchronization with the falling edge of the a4 output. figure 1.15.6. timing chart of operation (1) phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the "l" level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the ___ ___ values of timer b2, timer a4, and timer a4-1. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase of the former, have the corresponding timers work similarly to dealing with ___ the u and u phases to generate an intended waveform.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 116 figure 1.15.7. timing chart of operation (1) timer a4 output trigger signal for timer ai start (timer b2 overflow signal) timer b2 u phase dead time a carrier wave of triangular waveform carrier wave signal wave rewriting timer a4 every timer b2 interrupt occurres. u phase output signal m nn mp o note: set to triangular wave modulation mode and to three-phase mode 1. control signal for timer a4 reload m u phase u phase output signal timer b2 interrupt occurres. rewriting three-phase buffer register. assigning certain values to du0 (bit 0 at 030a 16 ) and dub0 (bit 1 at 030a 16 ), and to du1 (bit 0 at 030b 16 ) and dub1 (bit 1 at 030b 16 ) allows you to output the waveforms as shown in figure 1.15.7, that is, to ___ ___ output the u phase alone, to fix u phase to h, to fix the u phase to h, or to output the u phase alone.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 117 sawtooth modulation to generate a pwm waveform of sawtooth wave modulation, set 1 in the modulation mode select bit (bit 6 at 0308 16 ). also, set 0 in the timers a4, a1, and a2-1 control bit (bit 1 at 0309 16 ). in this mode, the timer registers of timers a4, a1, and of a2 comprise conventional timers a4, a1, and a2 alone, and reload the corresponding timer registers content to the counter every time the timer b2 counters content be- comes 0000 16 . the effective interrupt output specification bit (bit 1 at 0308 16 ) and the effective interrupt output polarity select bit (bit 0 at 0308 16 ) go nullified. an example of u phase waveform is shown in figure 75, and the description of waveform output workings is given below. set 1 in du0 (bit 0 at 030a 16 ), and set 0 in dub0 (bit 1 at 030a 16 ). in addition, set 0 in du1 (bit 0 at 030b 16 ) and set 1 in dub1 (bit 1 at 030b 16 ). when the timber b2 counters content becomes 0000 16 , timer b2 generates an interrupt, and timer a4 starts outputting one-shot pulses at the same time. in this instance, the contents of the three-phase buffer registers du1 and du0 are set in the three-phase output shift register (u phase), and the contents of dub1 and dub0 are set in the three-phase output register (u phase). after this, the three-phase buffer registers content is set in the three-phase shift register every time the timer b2 counters content be- comes 0000 16 . ___ the value of du0 and that of dub0 are output to the u terminal (p8 0 ) and to the u terminal (p8 1 ) respectively. when the timer a4 counter counts the value written to timer a4 (034f 16 , 034e 16 ) and when timer a4 finishes outputting one-shot pulses, the three-phase output shift registers content is shifted one ___ position, and the value of du1 and that of dub1 are output to the u phase output signal and to the u output signal respectively. at this time, one-shot pulses are output from the timer for setting dead time used for setting the time over which the l level of the u phase waveform doesnt lap over the l level of ___ the u phase waveform, which has the opposite phase of the former. the u phase waveform output that started from the h level keeps its level until the timer for setting dead time finishes outputting one-shot pulses even though the three-phase output shift registers content changes from 1 to 0 by the effect of the one-shot pulses. when the timer for setting dead time finishes outputting one-shot pulses, 0 already shifted in the three-phase shift register goes effective, and the u phase waveform changes to the l level. when the timer b2 counters content becomes 0000 16 , the contents of the three-phase buffer registers du1 and du0 are set in the three-phase shift register (u phase), and the contents of dub1 and ___ dub0 are set in the three-phase shift register (u phase) again. a u phase waveform is generated by these workings repeatedly. with the exception that the three-phase ___ ___ output shift register on the u phase side is used, the workings in generating a u phase waveform, which has the opposite phase of the u phase waveform, are the same as in generating a u phase waveform. in this way, a waveform can be picked up from the applicable terminal in a manner in which the l level of the u phase waveform doesnt lap over that of the u phase waveform, which has the opposite phase of the u phase waveform. the width of the l level too can be adjusted by varying the values of timer b2 ___ ___ and timer a4. in dealing with the v and w phases, and v and w phases, the latter are of opposite phase ___ of the former, have the corresponding timers work similarly to dealing with the u and u phases to gener- ate an intended waveform.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 118 timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform m n o p note: set to sawtooth modulation mode and to three-phase mode 0. interrupt occurres. rewriting the value of timer a4. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. trigger signal for timer ai start (timer b2 overflow signal) figure 1.15.8. timing chart of operation (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer three-phase motor control timers functions 119 timer b2 timer a4 output u phase u phase dead time carrier wave signal wave a carrier wave of sawtooth waveform mn p note: set to sawtooth modulation mode and to three- p hase mode 0. u phase output signal u phase output signal the three-phase shift register shifts in synchronization with the falling edge of timer a4. trigger signal for timer ai start (timer b2 overflow signal) interrupt occurres. rewriting the value of timer a4. rewriting three-phase output buffer register data transfer is made from the three- phase buffer register to the three- phase shift register in step with the timing of the timer b overflow. interrupt occurres. rewriting the value of timer a4. figure 1.15.9. timing chart of operation (3) ___ setting 1 both in dub0 and in dub1 provides a means to output the u phase alone and to fix the u phase output to h as shown in figure 1.15.9.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 120 serial i/o serial i/o is configured as five channels: uart0 to uart4. uart0 to 4 uart0 to uart4 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure 1.16.1 and 1.16.2 show the block diagram of uarti (i=0 to 4). figures 1.16.3 and 1.16.4 show the block diagram of the transmit/receive unit. uarti has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 and 02f8 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few functions are different, uart0 to uart4 have almost the same functions. uart2 to uart4, in particular, are compliant with the sim interface with some extra settings added in clock-asynchronous serial i/o mode (note). it also has the bus collision detection function that generates an interrupt request if the txd pin and the rxd pin are different in level. table 1.16.1 shows the comparison of functions of uart0 to uart4, and figures 1.16.5 through 1.16.11 show the registers related to uarti. note: sim : subscriber identity module note 1: only when clock synchronous serial i/o mode. note 2: only when clock synchronous serial i/o mode and 8-bit uart mode. note 3: only when uart mode. note 4: using for sim interface. uart0 uart1 uart2 function clk polarity selection continuous receive mode selection lsb first / msb first selection impossible transfer clock output from multiple pins selection impossible impossible impossible impossible serial data logic switch impossible sleep mode selection impossible impossible txd, rxd i/o polarity switch impossible possible cmos output txd, rxd port output format cmos output n-channel open drain output impossible parity error signal output impossible impossible bus collision detection impossible possible possible (note 1) separate cts/rts pins possible (note 1) possible (note 1) possible (note 3) possible (note 1) possible (note 1) possible (note 1) possible (note 1) possible (note 3) possible possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) uart3 impossible impossible impossible possible possible possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) uart4 impossible impossible impossible possible possible possible (note 1) possible (note 2) possible (note 1) possible (note 4) possible (note 4) cmos output cmos output table 1.16.1. comparison of functions of uart0 to uart4
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 121 figure 1.16.1. block diagram of uarti (i = 0 to 2) n0 : values set to uart0 bit rate generator (brg0) n1 : values set to uart1 bit rate generator (brg1) n2 : values set to uart2 bit rate generator (brg2) rxd2 reception control circuit transmission control circuit 1 / (n2+1) 1/16 1/16 1/2 bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk2 cts2 / rts2 f 1 f 8 f 32 vcc rts 2 cts 2 txd2 (uart2) rxd polarity reversing circuit txd polarity reversing circuit rxd0 1 / (n0+ 1) 1/2 clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk0 clock source selection cts0 / rts0 f 1 f 8 f 32 reception control circuit transmission control circuit internal external vcc rts 0 cts 0 txd0 transmit/ receive unit rxd1 1 / (n1+1) 1/16 1/16 1/2 clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk1 clock source selection f 1 f 8 f 32 reception control circuit transmission control circuit internal external rts 1 cts 1 txd1 (uart1) (uart0) clk polarity reversing circuit clk polarity reversing circuit cts/rts disabled cts/rts separated clock output pin select switch cts1 / rts1 / cts0 / clks1 cts/rts disabled cts0 from uart1 cts/rts selected cts/rts disabled v cc cts0 to uart0 cts 0 cts/rts disabled cts/rts separated cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit transmit/ receive unit 1/16 1/16 bit rate generator bit rate generator
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 122 rxd3 reception control circuit transmission control circuit 1 / (n2+1) 1/16 1/16 1/2 bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk3 cts3 / rts3 f 1 f 8 f 32 vcc rts 3 cts 3 txd3 (uart3) rxd polarity reversing circuit txd polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit n3 : values set to uart3 bit rate generator (brg3) n4 : values set to uart4 bit rate generator (brg4) rxd4 reception control circuit transmission control circuit 1 / (n2+1) 1/16 1/16 1/2 bit rate generator clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk4 cts4 / rts4 f 1 f 8 f 32 vcc rts 4 cts 4 txd4 (uart4) rxd polarity reversing circuit txd polarity reversing circuit cts/rts disabled cts/rts disabled cts/rts selected clk polarity reversing circuit internal external clock source selection transmit/ receive unit figure 1.16.2. block diagram of uarti (i = 3, 4)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 123 figure 1.16.3. block diagram of uarti (i = 0, 1) transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 0366 16 address 0367 16 address 036e 16 address 036f 16 address 0362 16 address 0363 16 address 036a 16 address 036b 16 data bus low-order bits msb/lsb conversion circuit d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? data bus high-order bits
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 124 sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type data bus low-order bits txdi uarti transmit register par disabled par enabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 uart2 transmit buffer register uart (8 bits) uart (9 bits) clock synchronous type uarti receive buffer register uarti receive register 2sp 1sp uart (7 bits) uart (8 bits) uart(7 bits) uart (9 bits) clock synchronous type clock synchronous type rxdi uart (8 bits) uart (9 bits) address 033e 16 address 033f 16 address 032e 16 address 032f 16 address 02fe 16 address 02ff 16 address 033a 16 address 033b 16 address 032a 16 address 032b 16 address 02fa 16 address 02fb 16 data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8 0000000 sp sp par ? reverse no reverse error signal output circuit rxd data reverse circuit error signal output enable error signal output disable reverse no reverse logic reverse circuit + msb/lsb conversion circuit logic reverse circuit + msb/lsb conversion circuit par enabled par disabled uart clock synchronous type txd data reverse circuit sp : stop bit par : parity bit i: 2 to 4 figure 1.16.4. block diagram of uarti (i = 2 to 4) transmit/receive unit
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 125 figure 1.16.5. serial i/o-related registers (1) b7 uarti bit rate generator b0 symbol address when reset u0brg 0361 16 indeterminate u1brg 0369 16 indeterminate u2brg 0339 16 indeterminate u3brg 0329 16 indeterminate u4brg 02f9 16 indeterminate function assuming that set value = n, brgi divides the count source by n + 1 00 16 to ff 16 values that can be set w r a a b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmit data nothing is assigned. when write, set "0". when read, their contents are indeterminate. symbol address when reset u0tb 0363 16 , 0362 16 indeterminate u1tb 036b 16 , 036a 16 indeterminate u2tb 033b 16 , 033a 16 indeterminate u3tb 032b 16 , 032a 16 indeterminate u4tb 02fb 16 , 02fa 16 indeterminate w r a a (b15) symbol address when reset u0rb 0367 16 , 0366 16 indeterminate u1rb 036f 16 , 036e 16 indeterminate u2rb 032f 16 , 032e 16 indeterminate u3rb 032f 16 , 032e 16 indeterminate u4rb 02ff 16 , 02fe 16 indeterminate b7 b0 (b8) b7 b0 uarti receive buffer register oer fer sum function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note 1: bits 15 through 12 are set to 0 when the serial i/o mode select bit (bits 2 to 0 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 and 02f8 16 ) are set to 000 2 or the receive enable bit is set to 0. (bit 15 is set to 0 when bits 14 to 12 all are set to 0.) bits 14 and 13 are also set to 0 when the lower byte of the uarti receive buffer register (addresses 0366 16 , 036e 16 , 033e 16 , 032e 16 and 02fe 16 ) is read out. note 2: arbitration lost detecting flag is allocated to u2rb, u3rb and u4rb and noting but 0 may be written. nothing is assigned in bit 11 of u0rb and u1rb. when write, set "0". when read, the value of this bit is 0. invalid invalid invalid per overrun error flag (note 1) framing error flag (note 1) parity error flag (note 1) error sum flag (note 1) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found nothing is assigned. when write, set "0". when read, the value of these bits is 0. receive data w r receive data a a a a a a a a abt arbitration lost detecting flag (note 2) invalid 0 : not detected 1 : detected a a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 126 uarti transmit/receive mode register symbol address when reset uimr(i=0,1) 0360 16 , 0368 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye slep parity enable bit 0 : internal clock 1 : external clock (note 2) stop bit length select bit odd/even parity select bit sleep select bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid must always be ? function (during uart mode) function (during clock synchronous serial i/o mode) uarti transmit/receive mode register symbol address when reset uimr (i=2 to 4) 0338 16 , 0328 16 , 02f8 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r must be fixed to 001 0 0 0 : serial i/o invalid 0 1 0 : (note) 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 ckdir smd1 smd0 serial i/o mode select bit smd2 internal/external clock select bit stps pry prye iopol parity enable bit 0 : internal clock 1 : external clock (note 3) stop bit length select bit odd/even parity select bit txd, rxd i/o polarity reverse bit 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse usually set to ? 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long 0 0 0 : serial i/o invalid 0 1 0 : inhibited 0 1 1 : inhibited 1 1 1 : inhibited b2 b1 b0 0 : internal clock 1 : external clock invalid valid when bit 6 = ? 0 : odd parity 1 : even parity invalid invalid 0 : no reverse 1 : reverse usually set to ? function (during uart mode) function (during clock synchronous serial i/o mode) a aa a aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a aa note 1: bit 2 to bit 0 are set to 010 2 when i 2 c mode is used. note 2: select clk output by the corresponding function select registers a, b and c. note 3: set the corresponding function select register a to the i/o port. note 1: select clk output by the corresponding function select registers a, b and c. note 2: set the corresponding function select register a to the i/o port. figure 1.16.6. serial i/o-related registers (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 127 function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled 0 : txdi pin is cmos output 1 : txdi pin is n-channel open drain output uform transfer format select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open drain output must always be ? bit name bit symbol must always be ? note 1: set the corresponding function select register a to i/o port, and port direction register to ?? note 2: select rts output using the corresponding function select registers a and b. 0 : cts/rts function enabled 1 : cts/rts function disabled aa aa a a aa aa a a aa a aa aa a aa a aa a aa a function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled 0 : txdi pin is cmos output 1 : txdi pin is n-channel open-drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = 0 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open-drain output must always be 0 bit name bit symbol note 1: set the corresponding function select register a to i/o port, and port direction register to 0. note 2: select rts output using the corresponding function select registers a and b. note 3: only clock synchronous serial i/o mode and 8-bit uart mode are valid. 0 : cts/rts function enabled 1 : cts/rts function disabled nothing is assigned. when write, set 0. when read, the value of this bit is 0. 0 : lsb first 1 : msb first aa a aa a aa a aa aa aa a aa a aa a uart2 transmit/receive control register 0 symbol address when reset u2c0 033c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 uarti transmit/receive control register 0 symbol address when reset uic0(i=0,1) 0364 16 , 036c 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 figure 1.16.7. serial i/o-related registers (3)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 128 figure 1.16.8. serial i/o-related registers (4) function (during uart mode) w r function (during clock synchronous serial i/o mode) txept clk1 clk0 crs crd nch ckpol brg count source select bit transmit register empty flag 0 : transmit data is output at falling edge of transfer clock and receive data is input at rising edge 1 : transmit data is output at rising edge of transfer clock and receive data is input at falling edge clk polarity select bit cts/rts function select bit cts/rts disable bit data output select bit 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 0 : lsb first 1 : msb first 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0 : cts/rts function enabled 1 : cts/rts function disabled 0 : txdi pin is cmos output 1 : txdi pin is n-channel open drain output uform transfer format select bit (note 3) 0 0 : f 1 is selected 0 1 : f 8 is selected 1 0 : f 32 is selected 1 1 : inhibited b1 b0 valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) valid when bit 4 = ? 0 : cts function is selected (note 1) 1 : rts function is selected (note 2) 0 : data present in transmit register (during transmission) 1 : no data present in transmit register (transmission completed) 0: txdi pin is cmos output 1: txdi pin is n-channel open drain output must always be ? bit name bit symbol note 1: set the corresponding function select register a to i/o port, and port direction register to ?? note 2: select rts output using the corresponding function select registers a and b. note 3: valid only in clock syncronous serial i/o mode and 8 bits uart mode. 0 : cts/rts function enabled 1 : cts/rts function disabled a a a a a a a a a a a a a a a a a a a a a uarti transmit/receive control register 0 symbol address when reset uic0(i=3,4) 032c 16 , 02fc 16 08 16 b7 b6 b5 b4 b3 b2 b1 b0 0 : lsb first 1 : msb first
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 129 figure 1.16.9. serial i/o-related registers (5) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 0365 16 , 036d 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register nothing is assigned. when write, set "0". when read, the value of these bits is ?? uarti transmit/receive control register 1 symbol address when reset uic1 (i=2 to 4) 033d 16 , 032d 16 , 02fd 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register uiirs uarti transmit interrupt cause select bit 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) 0 : transmit buffer empty (ti = 1) 1 : transmit is completed (txept = 1) uirrm uarti continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enabled data logic select bit 0 : no reverse 1 : reverse 0 : no reverse 1 : reverse uilch uiere error signal output enable bit must be fixed to ? 0 : output disabled 1 : output enabled a aa a a aa a a aa aa a aa a aa a aa a aa a a aa aa a a a must be fixed to 0
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 130 note: when using multiple pins to output the transfer clock, the following requirements must be met: ?uart1 internal/external clock select bit (bit 3 at address 0368 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 0370 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) rcsp uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : continuous receive mode disabled 1 : continuous receive mode enabled nothing is assigned. when write, set "0". when read, its content is indeterminate. 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) u0irs u1irs u0rrm u1rrm 0 : cts/rts shared pin 1 : cts/rts separated 0 : cts/rts shared pin 1 : cts/rts separated separate cts/rts bit a a a a a a a a a a a a a a uarti special mode register symbol address when reset uismr (i=2 to 4) 0337 16 , 0327 16 , 02f7 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss iic mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : iic mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxdi 0 : disabled 1 : enabled transmit start condition select bit must always be 0 0 : rising edge of transfer clock 1 : underflow signal of timer ai (note 2) auto clear function select bit of transmit enable bit a a a a a a a a a a a a a a a a a a 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. when write, set "0". when read, its content is indeterminate. note 1: nothing but "0" may be written. note 2: uart2 : timer a0 underflow signal, uart3 : timer a3 underflow signal, uart4 : timer a4 underflow signal. (note1) nothing is assigned. when write, set "0". when read, its content is indeterminate. must be fixed to 0 must be fixed to 0 figure 1.16.10. serial i/o-related registers (6)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 131 figure 1.16.11. serial i/o-related registers (7) uarti special mode register 2 symbol address when reset uismr2 (i=2 to 4) 0336 16 , 0326 16 , 02f6 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function iicm2 csc swc als iic mode select bit 2 scl wait output bit sda output stop flag clock synchronous bit 0 : nack/ack interrupt dma source - ack transfer to receive buffer at the rising edge of last bit of receive clock receive interrupt is occurred at the rising edge of last bit of receive clock 1 : uart transfer/receive interrupt dma source - uart receive transfer to receive buffer at the falling edge of last bit of receive clock receive interrupt is occurred at the falling edge of last bit of receive clock 0 : disabled 1 : enabled stc uarti initialize bit swc2 scl wait output bit 2 sda output inhibit bit sdhi shtc start/stop condition control bit a aa a aa a aa a aa a a aa aa a aa a a 0 : disabled 1 : enabled 0 : disabled 1 : enabled 0 : disabled 1 : enabled 0 : uarti clock 1 : 0 output 0 : enabled 1 : disabled (high impedance) must set to "1" in selecting iic mode. aa aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer serial i/o 132 figure 1.16.12. serial i/o-related registers (8) symbol address when reset u2smr3 0335 16 000xxxxx 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 symbol address when reset u3smr3 0325 16 00000000 2 u4smr3 02f5 16 00000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 sse ss port function enable bit 0: ss function disable 1: ss function enable 0: without fault error 1: with fault error ckph dinc nodc err clock phase set bit serial input port set bit clock output select bit 0: select txdi and rxdi (master mode) (note 5) 1: select stxdi and srxdi (slave mode) (note 6) 0: clki is cmos output 1: clki is n-channel open drain output fault error flag (note 3) (note 4) 0: without clock delay 1: with clock delay 000:without delay 001:2-cycle of 1/f(x in ) 010:3-cycle of 1/f(x in ) 011:4-cycle of 1/f(x in ) 100:5-cycle of 1/f(x in ) 101:6-cycle of 1/f(x in ) 110:7-cycle of 1/f(x in ) 111:8-cycle of 1/f(x in ) sda 2 (txd 2 ) digital delay time set bit (note 1,2) dl0 dl1 dl2 uart2 special mode register 3 note 1: these bits are used for sda 2 (txd 2 ) output digital delay when using uart2 for iic interface. otherwise, must set to "000". note 2: when external clock is selected, delay is increased approx. 100ns. uarti special mode register 3 (i=3,4) 000 :without delay 001 :2-cycle of 1/f(x in ) 010 :3-cycle of 1/f(x in ) 011 :4-cycle of 1/f(x in ) 100 :5-cycle of 1/f(x in ) 101 :6-cycle of 1/f(x in ) 110 :7-cycle of 1/f(x in ) 111 :8-cycle of 1/f(x in ) sdai(txd 2 ) digital delay time set bit (note 1,2) dl0 dl1 dl2 note 1: these bits are used for sda 2 (txd 2 ) output digital delay when using uart2 for i c interface. otherwise, must set to "000". note 2: when external clock is selected, delay is increased approx. 100ns. note 3: set ss function after setting cts/rts disable bit (bit 4 of uarti transfer/receive control register 0) to "1". note 4: nothing but "0" may be written. note 5: set clki and txdi both for output using the clki and txdi function select register a. set the rxdi function select register a for input/output port and the port direction register to "0". note 6: set stxdi for output using the stxdi function select registers a and b. set the clki and srxdi function select register a for input/output port and the port direction register to "0". b7 b6 b5 b7 b6 b5 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 133 (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. tables 1.17.1 and 1.17.2 list the specifications of the clock synchronous serial i/o mode. figure 1.17.1 shows the uarti transmit/receive mode register. table 1.17.1. specifications of clock synchronous serial i/o mode (1) item specification transfer data format ? transfer data length: 8 bits transfer clock ? when internal clock is selected (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 = 0) : fi/ 2(n+1) (note 1) fi = f1, f8, f32 _ clk is selected by the corresponding port function select register, periph- eral function select register and peripheral subfunction select register. ? when external clock is selected (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 = 1) : input from clki pin _ set the corresponding function select register a to i/o port transmission/reception control _______ _______ _______ _______ ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 _______ _______ _ when cts function selected, cts input level = l _ clk selected by the corresponding port function select register, peripheral function select register and peripheral subfunction select register. ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1: clki input level = l reception start condition ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit enable bit (bit 0 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0, 1 at address 0370 16 , bit 4 at address 033d 16 , 032d 16 , 02fd 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0, 1 at address 0370 16 , bit 4 at address 033d 16 , 032d 16 , 02fd 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 134 item specification error detection ? overrun error (note 2) this error occurs when the next data is ready before contents of uarti receive buffer register are read out select function ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection (uart1) (note) uart1 transfer clock can be chosen by software to be output from one of the two pins set _______ _______ ? separate cts/rts pins (uart0) (note) _______ _______ uart0 cts and rts pins each can be assigned to separate pins ? switching serial data logic (uart2 to uart4) whether to reverse data in writing to the transmission buffer register or reading the reception buffer register can be selected. ? txd, rxd i/o polarity reverse (uart2 to uart4) this function is reversing txd port output and rxd port input. all i/o data level is reversed. table 1.17.2. specifications of clock synchronous serial i/o mode (2) _______ _______ note: the transfer clock output from multiple pins and the separate cts/rts pins functions cannot be selected simultaneously.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 135 figure 1.17.1. uarti transmit/receive mode register in clock synchronous serial i/o mode symbol address when reset uimr(i=0,1) 0360 16 , 0368 16 00 16 ckdir uarti transmit/receive mode registers internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock (note 2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be ??in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode ckdir uart2 transmit/receive mode register internal/external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock (note 3) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode txd, rxd i/o polarity reverse bit (note) 0 : no reverse 1 : reverse a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: usually set to 0. note 2: select clk output by the corresponding function select registers a, b and c. note 3: set the corres p ondin g function select re g ister a to the i/o p ort. note 1: select clk output by the corresponding function select registers a, b and c. note 2: set the corresponding function select register a to the i/o port. symbol address when reset uimr (i=2 to 4) 0338 16 , 0328 16 , 02f8 16 00 16
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 136 table 1.17.3 lists the functions of the input/output pins during clock synchronous serial i/o mode. this _______ table shows the pin functions when the transfer clock output from multiple pins and the separate cts/ _______ rts pins functions are not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open drain is selected, this pin is in floating state.) table 1.17.3. input/output pin functions in clock synchronous serial i/o mode pin name function method of selection txdi (p6 3 , p6 7 , p7 0 , p9 2 , p9 6 ) serial data output (note 1) serial data input (note 2) transfer clock output (note 1) transfer clock input (note 2) programmable i/o port (note 2) (outputs dummy data when performing reception only) rxdi (p6 2 , p6 6 , p7 1 , p9 1 , p9 7 ) clki (p6 1 , p6 5 , p7 2 , p9 0 , p9 5 ) internal/external clock select bit (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 ) = ? internal/external clock select bit (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 ) = ? port p6 1 , p6 5 , p7 2 , p9 0 and p9 5 direction register (bits 1 and 5 at address 03c2 16 , bit 2 at address 03c3 16 , bit 0 and 5 at address 03c7 16 ) = ? port p6 2 , p6 6 , p7 1 , p9 1 and p9 7 direction register (bits 2 and 6 at address 03c2 16 , bit 1 at address 03c3 16 , bit 1 and 7 at address 03c7 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) =?? cts/rts function select bit (bit 2 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ?? port p6 0 , p6 4 , p7 3 , p9 3 and p9 4 direction register (bits 0 and 4 at address 03c2 16 , bit 3 at address 03c3 16 , bits 3 and 4 at address 03c7 16 ) = ? cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16) = ?? cts/rts function select bit (bit 2 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ? cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ? cts input (note 2) rts output (note 1) ctsi/rtsi (p6 0 , p6 4 , p7 3 , p9 3 , p9 4 ) _______ _______ (when transfer clock output from multiple pins and separate cts/rts pins functions are not selected) ________ note 1: select txd output, clk output and rts output by the corresponding function select registers a, b and c. note 2: select i/o port by the corresponding function select register a.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 137 figure 1.17.2. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 tc t clk stopped pulsing because transfer enable bit = ? data is set in uarti transmit buffer register tc = tclk = 2(n + 1) / fi fi: frequency of brgi count source (f 1 , f 8 , f 32 ) n: value set to brgi transfer clock transmit enable bit (te) transmit buffer empty flag (tl) clki txdi transmit register empty flag (txept) ? ? ? ? ? ? ? ? ctsi the above timing applies to the following settings: ?internal clock is selected. ?cts function is selected. ?clk polarity select bit = ?? ?transmit interrupt cause select bit = ?? transmit interrupt request bit (ir) ? ? stopped pulsing because cts = ? transferred from uarti transmit buffer register to uarti transmit register shown in ( ) are bit symbols. cleared to ??when interrupt request is accepted, or cleared by software 1 / f ext dummy data is set in uarti transmit buffer register transmit enable bit (te) transmit buffer empty flag (tl) clki rxdi receive complete flag (rl) rtsi ? ? ? ? ? ? ? ? receive enable bit (re) ? ? receive data is taken in transferred from uarti transmit buffer register to uarti transmit register read out from uarti receive buffer register the above timing applies to the following settings: ?external clock is selected. ?rts function is selected. ?clk polarity select bit = ?? f ext : frequency of external clock transferred from uarti receive register to uarti receive buffer register receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 shown in ( ) are bit symbols. meet the following conditions are met when the clki input before data reception = ? ?transmit enable bit ? ?receive enable bit ? ?dummy data write to uarti transmit buffer register cleared to ??when interrupt request is accepted, or cleared by software ? example of receive timing (when external clock is selected)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 138 (a) polarity select function as shown in figure 1.17.3, the clk polarity select bit (bit 6 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) allows selection of the polarity of the transfer clock. ?when clk polarity select bit = ? note 2: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clk pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i figure 1.17.3. polarity of transfer clock (b) lsb first/msb first select function as shown in figure 1.17.4, when the transfer format select bit (bit 7 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure 1.17.4. transfer format lsb first ?when transfer format select bit = ? d0 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 t x d i r x d i clk i msb first note: this applies when the clk polarity select bit = ??
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 139 (c) transfer clock output from multiple pins function (uart1) this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the port function select register (bits of related to-p6 4 and p6 5 ). (see figure 1.17.5.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when _______ _______ this function is selected, uart1 cts/rts function cannot be used. figure 1.17.5. the transfer clock output from the multiple pins function usage microcomputer t x d 1 (p6 7 ) clks 1 (p6 4 ) clk 1 (p6 5 ) in clk in clk note: this applies when the internal clock is selected and transmission is performed only in clock synchronous serial i/o mode. (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 0370 16 , bit 5 at address 033d 16 , 032d 16 , 02fd 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. _______ _______ (e) separate cts/rts pins function (uart0) this function works the same way as in the clock asynchronous serial i/o (uart) mode. the method of setting and the input/output pin functions are both the same, so refer to select function in the next section, (2) clock asynchronous serial i/o (uart) mode. note that this function is invalid if the transfer clock output from the multiple pins function is selected. (f) serial data logic switch function (uart2 to uart4) when the data logic select bit (bit6 at address 033d 16 , 032d 16 , 02fd 16 ) = 1, and writing to transmit buffer register or reading from receive buffer register, data is reversed. figure 1.17.6 shows the example of serial data logic switch timing. figure 1.17.6. serial data logic switch timing d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 transfer clock txd i (no reverse) txd i (reverse) ? ? ? ? ? ? ?hen lsb first
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 140 item specification transfer data format ? character bit (transfer data): 7 bits, 8 bits, or 9 bits as selected ? start bit: 1 bit ? parity bit: odd, even, or nothing as selected ? stop bit: 1 bit or 2 bits as selected transfer clock ? when internal clock is selected (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 =1) : f ext /16(n+1)(note 1) (note 2) transmission/reception control _______ _______ _______ _______ ? cts function/rts function/cts, rts function chosen to be invalid transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 0 _______ _______ - when cts function selected, cts input level = l - txd output is selected by the corresponding port function select register, peripheral function select register and peripheral subfunction select register. reception start condition ? to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 0365 16 , 036d 16 , 033d 16 , 032d 16 , 02fd 16 ) = 1 - start bit detection interrupt request ? when transmitting generation timing - transmit interrupt cause select bits (bits 0,1 at address 0370 16 , bit 4 at address 033d 16 , 032d 16 , 02fd 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 0370 16 , bit 4 at address 033d 16 , 032d 16 , 02fd 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed (2) clock asynchronous serial i/o (uart) mode the uart mode allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables 1.18.1 and 1.18.2 list the specifications of the uart mode. figure 1.18.1 shows the uarti transmit/receive mode register. table 1.18.1. specifications of uart mode (1) note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: fext is input from the clki pin.
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 141 table 1.18.2. specifications of uart mode (2) item specification error detection ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ? framing error this error occurs when the number of stop bits set is not detected ? parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ? error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function _______ _______ ? separate cts/rts pins (uart0) _______ _______ uart0 cts and rts pins each can be assigned to separate pins ? sleep mode selection (uart0, uart1) this mode is used to transfer data to and from one of multiple slave micro- computers ? serial data logic switch (uart2 to uart4) this function is reversing logic value of transferring data. start bit, parity bit and stop bit are not reversed. ? txd, rxd i/o polarity switch (uart2 to uart4) this function is reversing txd port output and rxd port input. all i/o data level is reversed. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 142 figure 1.18.1. uarti transmit/receive mode register in uart mode symbol address when reset uimr(i=0,1) 0360 16 , 0368 16 00 16 ckdir uarti transmit / receive mode registers internal / external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit sleep select bit ckdir uarti transmit / receive mode register internal / external clock select bit stps pry prye iopol 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : no reverse 1 : reverse 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd / even parity select bit parity enable bit txd, rxd i/o polarity reverse bit (note) a aa a aa a a aa aa a a aa aa a a aa aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a a aa aa a a aa aa note: usually set to 0. symbol address when reset uimr (i=2 to 4) 0338 16 , 0328 16 , 02f8 16 00 16
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 143 table 1.18.3 lists the functions of the input/output pins during uart mode. this table shows the pin _______ _______ functions when the separate cts/rts pins function is not selected. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open drain is selected, this pin is in floating state.) table 1.18.3. input/output pin functions in uart mode pin name function method of selection serial data output (note 1) serial data input (note 2) programmable i/o port (note 2) transfer clock input (note 2) programmable i/o port internal/external clock select bit (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 ) = ? internal/external clock select bit (bit 3 at addresses 0360 16 , 0368 16 , 0338 16 , 0328 16 , 02f8 16 ) = ?? port p6 1 , p6 5 , p7 2 , p9 0 and p9 5 direction register (bits 1 and 5 at address 03c2 16 , bit 2 at address 03c3 16 , bits 0 and 5 at address 03c7 16 ) = ? port p6 2 , p6 6 , p7 1 , p9 1 and p9 7 direction register (bits 2 and 6 at address 03c2 16 , bit 1 at address 03c3 16 , bit 1 and 7 at address 03c7 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) =?? cts/rts function select bit (bit 2 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ?? port p6 0 , p6 4 , p7 3 , p9 3 and p9 4 direction register (bits 0 and 4 at address 03c2 16 , bit 3 at address 03c3 16 , bits 3 and 4 at address 03c7 16 ) = ? cts input (note 2) rts output txdi (p6 3 , p6 7 , p7 0 , p9 2 , p9 6 ) rxdi (p6 2 , p6 6 , p7 1 , p9 1 , p9 7 ) clki (p6 1 , p6 5 , p7 2 , p9 0 , p9 5 ) ctsi/rtsi (p6 0 , p6 4 , p7 3 , p9 3 , p9 4 ) cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16) = ?? cts/rts function select bit (bit 2 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ? cts/rts disable bit (bit 4 at addresses 0364 16 , 036c 16 , 033c 16 , 032c 16 , 02fc 16 ) = ? (note 1) (note 2) ________ _______ (when separate cts/rts pins function is not selected) ________ note 1: select txd output, clk output and rts output by the corresponding function select registers a, b and c. note 2: select i/o port by the corresponding function select register a.
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 144 transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) start bit parity bit txdi ctsi the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?cts function is selected. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? cleared to ??when interrupt request is accepted, or cleared by software transmit enable bit(te) transmit buffer empty flag(ti) txdi transmit register empty flag (txept) ? ? ? ? ? ? the above timing applies to the following settings : ?parity is disabled. ?two stop bits. ?cts function is disabled. ?transmit interrupt cause select bit = ?? transfer clock tc tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? shown in ( ) are bit symbols. shown in ( ) are bit symbols. tc transfer clock d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 sp st p sp d 0 d 1 st stopped pulsing because transmit enable bit = ? stop bit transferred from uarti transmit buffer register to uarti transmit register start bit the transfer clock stops momentarily as cts is ??when the stop bit is checked. the transfer clock starts as the transfer starts immediately cts changes to ?? data is set in uarti transmit buffer register d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st sp d 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st d 8 d 0 d 1 st sp sp transferred from uarti transmit buffer register to uarti transmit register stop bit stop bit data is set in uarti transmit buffer register. ? sp cleared to ??when interrupt request is accepted, or cleared by software ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure 1.18.2. typical transmit timings in uart mode
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 145 ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure 1.18.3. typical receive timing in uart mode _______ _______ (a) separate cts/rts pins function (uart0) _______ _______ _______ with the separate cts/rts bit (bit 6 at address 0370 16 ) is set to 1, the unit outputs/inputs the cts _______ and rts signals on different pins. (see figure 1.18.4.) this function is valid only for uart0. note _______ _______ that if this function is selected, the cts/rts function for uart1 cannot be used. _______ _______ _______ _______ set both cts/rts function select bit (bit 2 at address 0364 16 ) and cts/rts disable bit (bit 4 at address 0364 16 ) to "0" and set p6 4 to input port by the function select register. (b) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 0360 16 , 0368 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0. d 0 start bit sampled ? receive data taken in brgi count source receive enable bit rxdi transfer clock receive complete flag rtsi stop bit ? ? ? ? ? ? the above timing applies to the following settings : ?arity is disabled. ?ne stop bit. ?ts function is selected. receive interrupt request bit ? ? transferred from uarti receive register to uarti receive buffer register reception triggered when transfer clock is generated by falling edge of start bit d 7 d 1 cleared to ??when interrupt request is accepted, or cleared by software microcomputer t x d 0 (p6 3 ) r x d 0 (p6 2 ) in out cts rts cts0 (p6 4 ) rts0 (p6 0 ) ic _______ _______ figure 1.18.4. the separate cts/rts pins function usage
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 146 (c) function for switching serial data logic (uart2 to uart4) when the data logic select bit (bit 6 of address 033d 16 , 032d 16 , 02fd 16 ) is assigned 1, data is inverted in writing to the transmission buffer register or reading the reception buffer register. figure 1.18.5 shows the example of timing for switching serial data logic. figure 1.18.5. timing for switching serial data logic st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st sp st d3 d4 d5 d6 d7 p d0 d1 d2 transfer clock txd i (no reverse) txd i (reverse) ? ? ? ? ? ? ?when lsb first, parity enabled, one stop bit (d) txd, rxd i/o polarity reverse function (uart2 to uart4) this function is to reverse txd pin output and rxd pin input. the level of any data to be input or output (including the start bit, stop bit(s), and parity bit) is reversed. set this function to 0 (not to reverse) for usual use. (e) bus collision detection function (uart2 to uart4) this function is to sample the output level of the txd pin and the input level of the rxd pin at the rising edge of the transfer clock; if their values are different, then an interrupt request occurs. figure 1.18.6 shows the example of detection timing of a buss collision (in uart mode). figure 1.18.6. detection timing of a bus collision (in uart mode) st : start bit sp : stop bit st st sp sp transfer clock txd i rxd i bus collision detection interrupt request signal ? ? ? ? ? ? ? ? bus collision detection interrupt request bit ? ?
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 147 item specification transfer data format ? transfer data 8-bit uart mode (bit 2 to 0 of addresses 0338 16 , 0328 16 , 02f8 16 = 101 2 ) ? one stop bit (bit 4 of addresses 0338 16 , 0328 16 , 02f8 16 = 0) ? with the direct format chosen set parity to even (bit 5 and 6 of addresses 0338 16 , 0328 16 , 02f8 16 = 1 and 1 respectively) set data logic to direct (bit 6 of address 033d 16 = 0). set transfer format to lsb (bit 7 of address 033c 16 = 0). ? with the inverse format chosen set parity to odd (bit 5 and 6 of addresses 0338 16 , 0328 16 , 02f8 16 = 0 and 1 respectively) set data logic to inverse (bit 6 of address 033d 16 = 1) set transfer format to msb (bit 7 of address 033c 16 = 1) transfer clock ? with the internal clock chosen (bit 3 of addresses 0338 16 , 0328 16 , 02f8 16 = 0) : fi / 16 (n + 1) (note 1) : fi=f 1 , f 8 , f 32 ? with an external clock chosen (bit 3 of addresses 0338 16 , 0328 16 , 02f8 16 = 1) : f ext / 16 (n+1) (note 1) (note 2) transmission / reception control _______ _______ ? disable the cts and rts function (bit 4 of address 033c 16 , 032c 16 , 02fc 16 = 1) other settings ? the sleep mode select function is not available for uart2 ? set transmission interrupt factor to transmission completed (bit 4 of address 033d 16 , 032d 16 , 02fd 16 = 1) ? set n-channel open drain output to txd and rxd pins in uart3 and 4 (bit 5 of address 032c 16 , 02fc 16 = 1) transmission start condition ? to start transmission, the following requirements must be met: - transmit enable bit (bit 0 of address 033d 16 , 032d 16 , 02fd 16 ) = 1 - transmit buffer empty flag (bit 1 of address 033d 16 , 032d 16 , 02fd 16 ) = 0 reception start condition ? to start reception, the following requirements must be met: - reception enable bit (bit 2 of address 033d 16 , 032d 16 , 02fd 16 ) = 1 - detection of a start bit ? when transmitting when data transmission from the uart2 to uart4 transfer register is completed (bit 4 of address 033d 16 , 032d 16 , 02fd 16 = 1) ? when receiving when data transfer from the uart2 to uart4 receive register to the uart2 to uart4 receive buffer register is completed error detection ? overrun error (see the specifications of clock-asynchronous serial i/o) (note 3) ? framing error (see the specifications of clock-asynchronous serial i/o) ? parity error (see the specifications of clock-asynchronous serial i/o) - on the reception side, an l level is output from the txd i pin by use of the parity error signal output function (bit 7 of address 033d 16 , 032d 16 , 02fd 16 = 1) when a parity error is detected - on the transmission side, a parity error is detected by the level of input to the rxd i pin when a transmission interrupt occurs ? the error sum flag (see the specifications of clock-asynchronous serial i/o) (3) clock-asynchronous serial i/o mode (compliant with the sim interface) the sim interface is used for connecting the microcomputer with a memory card i/c or the like; adding some extra settings in uart2 to uart4 clock-asynchronous serial i/o mode allows the user to effect this function. table 1.19.1 shows the specifications of clock-asynchronous serial i/o mode (compliant with the sim interface). interrupt request generation timing note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. table 1.19.1. specifications of clock-asynchronous serial i/o mode (compliant with the sim interface)
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 148 figure 1.19.1. typical transmit/receive timing in uart mode (compliant with the sim interface) transmit enable bit(te) transmit buffer empty flag(ti) transmit register empty flag (txept) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi transmit interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p shown in ( ) are bit symbols. tc transfer clock sp stop bit data is set in uarti transmit buffer register sp a ??level returns from sim card due to the occurrence of a parity error. the level is detected by the interrupt routine. the level is detected by the interrupt routine. receive enable bit (re) receive complete flag (ri) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p start bit parity bit txd i the above timing applies to the following settings : ?parity is enabled. ?one stop bit. ?transmit interrupt cause select bit = ?? ? ? ? ? tc = 16 (n + 1) / fi or 16 (n + 1) / f ext fi : frequency of brgi count source (f 1 , f 8 , f 32 ) f ext : frequency of brgi count source (external clock) n : value set to brgi receive interrupt request bit (ir) ? ? d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp shown in ( ) are bit symbols. tc transfer clock sp stop bit a ??level returns from txd 2 due to the occurrence of a parity error. rxd i read to receive buffer read to receive buffer d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p signal conductor level (note 1) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 st p sp sp txd i rxd i signal conductor level (note 1) note: equal in waveform because txd i and rxd i are connected. transferred from uarti transmit buffer register to uarti transmit register cleared to ??when interrupt request is accepted, or cleared by software cleared to ??when interrupt request is accepted, or cleared by software note: after writing to the transfer buffer at above timing, transmission starts at the timing of brg overflow. (note)
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 149 (a) function for outputting a parity error signal with the error signal output enable bit (bit 7 of address 033d 16 , 032d 16 ) assigned 1, you can output an l level from the txd i pin when a parity error is detected. in step with this function, the generation timing of a transmission completion interrupt changes to the detection timing of a parity error signal. figure 1.19.2 shows the output timing of the parity error signal. figure 1.19.2. output timing of the parity error signal st : start bit p : even parity sp : stop bit d0 d1 d2 d3 d4 d5 d6 d7 p sp st hi-z transfer clock rxd i txd i receive complete flag ? ? ? ? ? ? ? ?lsb first ? (b) direct format/inverse format connecting the sim card allows you to switch between direct format and inverse format. if you choose the direct format, d0 data is output from txdi. if you choose the inverse format, d7 data is inverted and output from txdi. figure 1.19.3 shows the sim interface format. figure 1.19.3. sim interface format p : even parity d0 d1 d2 d3 d4 d5 d6 d7 p transfer clcck txd i (direct) txd i (inverse) d7 d6 d5 d4 d3 d2 d1 d0 p
clock asynchronous serial i/o (uart) mode under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer 150 figure 1.19.4 shows the example of connecting the sim interface. connect txdi and rxdi and apply pull- up. figure 1.19.4. connecting the sim interface microcomputer sim card txd i rxd i (note) note :txd pin is n-channel open drain and needs a pull-up resistance.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 151 uarti special mode register (i = 2 to 4) uart2 to uart4 operate the iic bus interface (simple iic bus) using the uarti special mode register (addresses 0337 16 , 0327 16 and 02f7 16 [i = 2 to 4]) and uarti special mode register 2 (addresses 0336 16 , 0326 16 and 02f6 16 [i = 2 to 4]). uart3 and uart4 add special functions using uarti special mode resister 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]). (1) iic bus interface mode the iic bus interface mode is provided with uart2 to uart4. table 1.20.1 shows the construction of the uarti special mode register and uarti special mode regis- ter 2. when the ic mode select bit (bit 0 in addresses 0337 16 , 0327 16 and 02f7 16 ) is set to 1, the i 2 c bus (simple i 2 c bus) interface circuit is enabled. table 1.20.1 shows the relationship of the iic mode select bit to control. to use the chip in the clock synchronized serial i/o mode or clock asynchronized serial i/o mode, always set this bit to 0. function normal mode i 2 c mode (note 1) factor of interrupt number 33, 35, 37 (note 2) uarti transmission no acknowledgment detection (nack) factor of interrupt number 34, 36, 38 (note 2) uarti reception start condition detection or stop condition detection uarti transmission output delay not delayed delayed p7 0 , p9 2 , p9 6 at the time when uarti is in use txd i (output) sdai (input/output) (note 3) p7 1 , p9 1 , p9 7 at the time when uarti is in use rxd i (input) scli (input/output) p7 2 , p9 0 , p9 5 at the time when uarti is in use clki p7 2 , p9 0 , p9 5 dma1 factor at the time when 1 1 0 1 is assigned to the dma request factor selection bits uarti reception acknowledgment detection (ack) noise filter width 15ns 50ns reading p7 1 , p9 1 , p9 7 reading the terminal when 0 is assigned to the direction register reading the terminal regardless of the value of the direction register 1 2 3 4 5 6 7 8 9 note 1: make the settings given below when i 2 c mode is in use. set 0 1 0 in bits 2, 1, 0 of the uarti transmission/reception mode register. disable the rts/cts function. choose the msb first function. note 2: follow the steps given below to switch from a factor to another. 1. disable the interrupt of the corresponding number. 2. switch from a factor to another. 3. reset the interrupt request flag of the corresponding number. 4. set an interrupt level of the corresponding number. note 3: set an initial value of sda transmission output when iic mode (iic mode select bit = "1") is valid and serial i/o is in valid. factor of interrupt number 39 to 41 (note 2) bus collision detection acknowledgment detection (ack) 10 initial value of uarti output h level (when 0 is assigned to the clk polarity select bit) the value set in latch p7 0 , p9 2 , p9 6 when the port is selected (note 3) 11 table 1.20.1. features in i 2 c mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 152 uarti special mode register b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) abscs acse sss i c mode select bit bus busy flag 0 : stop condition detected 1 : start condition detected scll sync output enable bit bus collision detect sampling clock select bit arbitration lost detecting flag control bit 0 : normal mode 1 : i c mode 0 : update per bit 1 : update per byte iicm abc bbs lsyn 0 : ordinary 1 : falling edge of rxdi 0 : disabled 1 : enabled transmit start condition select bit must always be ? 0 : rising edge of transfer clock 1 : underflow signal of timer ai auto clear function select bit of transmit enable bit a a a a a a a a a a a a a a a a a a 0 : no auto clear function 1 : auto clear at occurrence of bus collision must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 must always be 0 nothing is assigned. this bit can neither be set nor reset. when read, its content is indeterminate. note 1: nothing but "0" may be written. note 2: uart2 : timer a0 underflow signal, uart3 : timer a3 underflow signal, uart4 : timer a4 underflow signal. (note 1) 2 2 (note 2) symbol address when reset uismr (i=2 to 4) 0337 16 , 0327 16 , 02f7 16 00 16 uarti special mode register 2 symbol address when reset uismr2 (i=2 to 4) 0336 16 , 0326 16 , 02f6 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function iicm2 csc swc als iic mode select bit 2 scl wait output bit sda output stop flag clock synchronous bit refer to table 1.20.2. 0 : disabled 1 : enabled stc uarti initialize bit swc2 scl wait output bit 2 sda output inhibit bit sdhi shtc start/stop condition control bit a a a a a a a a a a a a a a a a a 0 : disabled 1 : enabled 0 : disabled 1 : enabled 0 : disabled 1 : enabled 0 : uarti clock 1 : 0 output 0 : enabled 1 : disabled (high impedance) must set to "1" in selecting iic mode. a a a figure 1.20.1. uart2 special mode register
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 153 selector i/o timer delay uart2 reception register external clock arbitration start condition detection stop condition detection falling edge detection uart2 transmission/nack interrupt request uart2 reception/ack interrupt request dmai request 9th pulse port reading * with iicm set to 1, the port terminal is to be readable even if 1 is assigned to p7 1 of the direction register. l-synchronous output enabling bit bus collision/start, stop condition detection interrupt request bus collision detection noize filter i/0 noize filter p7 0 /txd 2 /sda p7 1 /rxd 2 /scl clk control internal clock uart2 serector uart2 i/0 timer p7 2 /clk 2 data register d t q d t q d t q nack ack uart2 uart2 r iicm=1 iicm=0 iicm=1 iicm=0 iicm=1 and iicm2=0 iicm=0 iicm=1 iicm=1 iicm=0 s r q bus busy iicm=1 iicm=0 als r s swc falling edge of 9th pulse iicm=1 and iicm2=0 iicm=0 or iicm2=1 iicm=0 or iicm2=1 swc2 sdhi to dmai to dmai selector transmission register uart2 noize filter figure 1.20.2. functional block diagram for i 2 c mode figure 1.20.2 is a block diagram of the iic bus interface. to explain the control bit of the iic bus interface, uart2 is used as an example. uart2 special mode register (address 0337 16 ) bit 0 is the iic mode select bit. when set to 1, ports p7 0 , p7 1 and p7 2 operate respectively as the sda2 data transmission-reception pin, scl2 clock i/o pin and port p7 2 . a delay circuit is added to sda2 transmission output, therefore after scl2 is sufficiently l level, sda2 output changes. port p7 1 (scl2) is designed to read pin level regardless of the content of the port direction register. sda2 transmission output is initially set to port p7 0 in this mode. furthermore, interrupt factors for the bus collision detection interrupt, uart2 transmission interrupt and uart2 reception interrupt change respectively to the start/stop condition detection interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 154 the start condition detection interrupt is generated when the fall at the sda2 pin (p7 0 ) is detected while the scl2 pin (p7 1 ) is in the h state. the stop condition detection interrupt is generated when the rise at the sda2 pin (p7 0 ) is detected while the scl2 pin (p7 1 ) is in the h state. the acknowledge non-detection interrupt is generated when the h level at the sda2 pin is detected at the 9th rise of the transmission clock. the acknowledge detection interrupt is generated when the l level at the sda2 pin is detected at the 9th rise of the transmission clock. also, dma transfer can be started when the acknowledge is de- tected if uart2 transmission is selected as the dma1 request factor. bit 2 is the bus busy flag. it is set to 1 when the start condition is detected, and reset to 0 when the stop condition is detected. bit 1 is the arbitration lost detection flag control bit. arbitration detects a conflict between data trans- mitted at scl2 rise and data at the sda2 pin. this detection flag is allocated to bit 3 in uart2 transmission buffer register 1 (address 033f 16 ). it is set to 1 when a conflict is detected. with the arbitration lost detection flag control bit, it can be selected to update the flag in units of bits or bytes. when this bit is set to 1, update is set to units of byte. if a conflict is then detected, the arbitration lost detection flag control bit will be set to 1 at the 9th rise of the clock. when updating in units of byte, always clear (0 interrupt) the arbitration lost detection flag control bit after the 1st byte has been acknowledged but before the next byte starts transmitting. bit 3 is the scl2 l synchronization output enable bit. when this bit is set to 1, the p7 1 data register is set to 0 in sync with the l level at the scl2 pin. bit 4 is the bus collision detection sampling clock select bit. the bus collision detection interrupt is generated when rxdi and txdi level do not conflict with one another. when this bit is 0, a conflict is detected in sync with the rise of the transfer clock. when this bit is 1, detection is made when timer ai (timer a0 with uart2, timer a3 with uart3 and timer a4 with uart4) underflows. operation is shown in figure 1.20.3. bit 5 is the transmission enable bit automatic clear select bit. by setting this bit to 1, the transmission bit is automatically reset to 0 when the bus collision detection interrupt factor bit is 1 (when a conflict is detected). bit 6 is the transmission start condition select bit. by setting this bit to 1, txdi transmission starts in sync with the rise at the rxdi pin.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 155 1. bus collision detect sampling clock select bit (bit 4 of the uarti special mode register) 0: rising edges of the transfer clock clki timer ai 1: timer a0 underflow 2. auto clear function select bit of transmit enable bit (bit 5 of the uarti special mode register) clki txdi/rxdi bus collision detect interrupt request bit transmit enable bit 3. transmit start condition select bit (bit 6 of the uarti special mode register) clki txdi enabling transmission clki txdi rxdi with "1: falling edge of rxd i " selected 0: in normal state txdi/rxdi figure 1.20.3. some other functions added
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 156 uart2 special mode register 2 (address 0336 16 ) bit 0 is the iic mode select bit. table 1.20.2 gives control changes by bit when the iic mode select bit is 1. start and stop condition detection timing characteristics are shown in figure 1.20.4. always set bit 7 (start/stop condition control bit) to 1. bit 1 is the clock synchronization bit. when this bit is set to 1, if the rise edge is detected at pin scl2 while the internal scl is h level, the internal scl is changed to l level, the baud rate generator value is reloaded and the l sector count starts. also, while the scl2 pin is l level, if the internal scl changes from l level to h, baud rate generator stops counting. if the scl2 pin is h level, counting restarts. because of this function, the uart2 transmission-reception clock takes the and condition for the internal scl and scl2 pin signals. this function operates from the clock half period before the 1st rise of the uart2 clock to the 9th rise. to use this function, select the internal clock as the transfer clock. bit 2 is the scl wait output bit. when this bit is set to 1, output from the scl2 pin is fixed to l level at the clocks 9th rise. when set to 0, the l output lock is released. bit 3 is the sda output stop bit. when this bit is set to 1, an arbitration lost is generated. if the arbitration lost detection flag is 1, the sda2 pin simultaneously becomes high impedance. bit 4 is the uart2 initialize bit. while this bit is set to 1, the following operations are performed when the start condition is detected. 1. the transmission shift register is initialized and the content of the transmission register is trans- mitted to the transmission shift register. as such, transmission starts with the 1st bit of the next input clock. however, the uart2 output value remains the same as when the start condition was detected, without changing from when the clock is input to when the 1st bit of data is output. 2. the reception shift register is initialized and reception starts with the 1st bit of the next input clock. 3. the scl wait output bit is set to 1. as such, the scl2 pin becomes l level at the rise of the 9th bit of the clock. when uart transmission-reception has been started using this function, the content of the transmis- sion buffer available flag does not change. also, to use this function, select an external clock as the transfer clock. bit 5 is scl wait output bit 2. when this bit is set to 1 and serial i/o has been selected, an l level can be forcefully output from the scl2 pin even during uart operation. when this bit is set to 0', the l output from the scl2 pin is canceled and the uart2 clock is input and output. bit 6 is the sda output disable bit. when this bit is set to 1, the sda2 pin is forcefully made high impedance. to overwrite this bit, do so at the rise of the uart2 transfer clock. the arbitration lost detection flag may be set.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 157 table 1.20.2. functions changed by i 2 c mode select bit 2 iicm 2 = 0 acknowrege not detect (nack) acknowrege detect (ack) acknowrege detect (ack) rising edge of the last bit of re- ceive clock rising edge of the last bit of re- ceive clock function interrupt no. 33, 35, 37 factor interrupt no. 34, 36, 38 factor dma factor data transfer timing from uarti (i = 2 to 4) receive shift register to re- ceive buffer uarti(i = 2 to 4) receive / ack in- terrupt request generation timing iicm 2 = 1 uart2 transfer (rising edge of ) acknowrege detect (ack) acknowrege detect (ack) rising edge of the last bit of re- ceive clock rising edge of the last bit of re- ceive clock set up time hold time scl sda (start condition) sda (stop condition) figure 1.20.4. start/stop condition detect timing characteristics 3 to 6 cycles < set up time (note) 3 to 6 cycles < hold time (note) note : cycle number shows main clock input oscillation frequency f(x in ) cycle number. uart2 special mode register 3 (address 0335 16 ) bits 5 to 7 are the sda2 digital delay setting bits. by setting these bits, it is possible to turn the sda2 delay off or set the f(x in ) delay to 2 to 8 cycles.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 158 p1 3 p1 2 ic1 p9 3( ss 3 ) p9 2( txd 3 ) p9 0( clk 3 ) p9 1( rxd 3 ) ic2 p9 3( ss 3 ) p9 2( srxd 3 ) p9 0( clk 3 ) p9 1( stxd 3 ) ic3 p9 3( ss 3 ) p9 2( srxd 3 ) p9 0( clk 3 ) p9 1( stxd 3 ) m16c/80 (m) m16c/80 (s) m16c/80 (s) m :master s :slave (2) serial interface special function _____ uart 3 and uart4 can control communications on the serial bus using the ssi input pins (figure 1.20.5). the master outputting the transfer clock transfers data to the slave inputting the transfer clock. in this case, in order to prevent a data collision on the bus, the master floats the output pin of other slaves/ _____ masters using the ssi input pins. figure 1.20.6 shows the structure of uarti special mode register 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]) which controls this mode. _____ ssi input pins function between the master and slave are as follows. figure 1.20.5 serial bus communication control example using the ssi input pins < slave mode (stxdi and srxdi are selected, dinc = 1) > _____ when an h level signal is input to an ssi input pin, the stxdi and srxdi pins both become high impedance, hence clock input is ignored. when an "l" level signal is input to an ssi input pin, clock input becomes effective and serial communications are enabled. (i = 3 or 4) < master mode (txdi and rxdi are selected, dinc = 0) > _____ _____ the ssi input pins are used with a multiple master system. when an ssi input pin is h level, transmis- _____ sion has priority and serial communications are enabled. when an l signal is input to an ssi input pin, another master exists, and the stxdi, srxdi and clki pins all become high impedance. moreover, the trouble error interrupt request bit becomes 1. communications do not stop even when a trouble error is generated during communications. to stop communications, set bits 0, 1 and 2 of the uarti transmission-reception mode register (address 0328 16 and 02f8 16 [i = 3 or 4]) to 0. the trouble error interrupt is used by both the bus collision interrupt and start/stop condition detection interrupts, but the trouble error interrupt itself can be selected by setting bit 0 of uarti special mode register 3 (address 0325 16 and 02f5 16 [i = 3 or 4]) to 1. when the trouble error flag is set to 0, output is restored to the clock output and data output pins. in _____ _____ the master mode, if an ssi input pin is h level, 0 can be written for the trouble error flag. when an ssi input pin is l level, 0 cannot be written for the trouble error flag. in the slave mode, the 0 can be _____ written for the trouble error flag regardless of the input to the ssi input pins.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 159 symbol address when reset u3smr3 0325 16 00000000 2 u4smr3 02f5 16 00000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 sse ss port function enable bit 0: ss function disable 1: ss function enable 0: without fault error 1: with fault error ckph dinc nodc err clock phase set bit serial input port set bit clock output select bit 0: select txdi and rxdi (master mode) (note 5) 1: select stxdi and srxdi (slave mode) (note 6) 0: clki is cmos output 1: clki is n-channel open drain output fault error flag (note 3) (note 4) 0: without clock delay 1: with clock delay uarti special mode register 3 (i=3,4) 000 :without delay 001 :2-cycle of 1/f(x in ) 010 :3-cycle of 1/f(x in ) 011 :4-cycle of 1/f(x in ) 100 :5-cycle of 1/f(x in ) 101 :6-cycle of 1/f(x in ) 110 :7-cycle of 1/f(x in ) 111 :8-cycle of 1/f(x in ) sdai(txd 2 ) digital delay time set bit (note 1,2) dl0 dl1 dl2 note 1: these bits are used for sda 2 (txd 2 ) output digital delay when using uart2 for i c interface. otherwise, must set to "000". note 2: when external clock is selected, delay is increased approx. 100ns. note 3: set ss function after setting cts/rts disable bit (bit 4 of uarti transfer/receive control register 0) to "1". note 4: nothing but "0" may be written. note 5: set clki and txdi both for output using the clki and txdi function select register a. set the rxdi function select register a for input/output port and the port direction register to "0". note 6: set stxdi for output using the stxdi function select registers a and b. set the clki and srxdi function select register a for input/output port and the port direction register to "0". b7 b6 b5 2 figure 1.20.6. uarti special mode register 3 (i=3,4)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 160 master ss input data output timing data input timing d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 "h" "l" clock output (ckpol=0, ckph=0) "h" "l" clock output (ckpol=1, ckph=0) "h" "l" clock output (ckpol=0, ckph=1) "h" "l" clock output (ckpol=1, ckph=1) "h" "l" "h" "l" clock phase setting with bit 1 of uarti special mode register 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]) and bit 6 of uarti transmission-reception control register 0 (addresses 032c 16 and 02fc 16 [i = 3 or 4]), four combinations of transfer clock phase and polarity can be selected. bit 6 of uarti transmission-reception control register 0 (addresses 032c 16 and 02fc 16 [i = 3 or 4]) sets transfer clock polarity, whereas bit 1 of uarti special mode register 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]) sets transfer clock phase. transfer clock phase and polarity must be the same between the master and slave involved in the transfer. < master (internal clock) (dinc = 0) > figure 1.20.7 shows the transmission and reception timing. < slave (external clock) (dinc = 1) > ? with 0 for bit 1 (ckph) of uarti special mode register 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]), when an ssi input pin is h level, output data is high impedance. when an ssi input pin is l level, the serial transmission start condition is satisfied, though output is indeterminate. after that, serial transmission is synchronized with the clock. figure 1.20.8 shows the timing. ? with 1 for bit 1 (ckph) of uarti special mode register 3 (addresses 0325 16 and 02f5 16 [i = 3 or 4]), when an ssi input pin is h level, output data is high impedance. when an ssi input pin is l level, the first data is output. after that, serial transmission is synchronized with the clock. figure 1.20.9 shows the timing. figure 1.20.7. the transmission and reception timing in master mode (internal clock)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer uarti special mode register 161 high- inpedance ss input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" high- inpedance d 0 d 1 d 2 d 3 d 4 d 6 d 7 d 5 indeterminate high- inpedance ss input clock input (ckpol=0, ckph=0) clock input (ckpol=1, ckph=0) data output timing data input timing "h" "l" "h" "l" "h" "l" "h" "l" high- inpedance d 0 d 1 d 2 d 3 d 6 d 7 d 4 d 5 figure 1.20.8. the transmission and reception timing (ckph=0) in slave mode (external clock) figure 1.20.9. the transmission and reception timing (ckph=1) in slave mode (external clock)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 162 item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) v cc = 5v f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? with sample and hold function (10-bit resolution) an 0 to an 7 input : 3lsb anex 0 and anex 1 input (including mode in which external operation amp is connected) : 7lsb v cc = 3v ? without sample and hold function (8-bit resolution) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8 pins (an 0 to an 7 ) + 2 pins (anex 0 and anex 1 ) a-d conversion start condition ? software trigger a-d conversion starts when the a-d conversion start flag changes to 1 ? external trigger (can be retriggered) a-d conversion starts when the a-d conversion start flag is 1 and the ___________ adtrg/p9 7 input changes from h to l conversion speed per pin ? without sample and hold function 8-bit resolution: 49 f ad cycles, 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles, 10-bit resolution: 33 f ad cycles a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 , p9 5 , and p9 6 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 0397 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 0397 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table 1.21.1 shows the performance of the a-d converter. figure 1.21.1 shows the block diagram of the a- d converter, and figures 1.21.2 and 1.21.3 show the a-d converter-related registers. note 1: does not depend on use of sample and hold function. note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. table 1.21.1. performance of a-d converter
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 163 figure 1.21.1. block diagram of a-d converter 1/2 f ad 1/2 f ad a-d conversion rate selection (0381 16 , 0380 16 ) (0383 16 , 0382 16 ) (0385 16 , 0384 16 ) (0387 16 , 0386 16 ) (0389 16 , 0388 16 ) (038b 16 , 038a 16 ) (038d 16 , 038c 16 ) (038f 16 , 038e 16 ) cks1=1 cks0=0 0 0 : normal operation 0 1 : anex0 1 0 : anex1 1 1 : external op-amp mode a-d register 0(16) a-d register 1(16) a-d register 2(16) a-d register 3(16) a-d register 4(16) a-d register 5(16) a-d register 6(16) a-d register 7(16) resistance ladder anex1 anex0 successive conversion register opa1,opa0=0,1 opa0=1 opa1=1 opa1,opa0=1,1 an 0 an 1 an 2 an 3 an 5 an 6 an 7 a-d control register 0 (address 0396 16 ) a-d control register 1 (address 0397 16 ) v ref v in data bus high-order data bus low-order v ref an 4 opa1,opa0=0,0 vcut=0 av ss vcut=1 cks0=1 cks1=0 ch2,ch1,ch0=000 ch2,ch1,ch0=001 ch2,ch1,ch0=010 ch2,ch1,ch0=011 ch2,ch1,ch0=100 ch2,ch1,ch0=101 ch2,ch1,ch0=110 ch2,ch1,ch0=111 decoder comparator opa1, opa0 addresses
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 164 figure 1.21.2. a-d converter-related registers (1) a-d control register 0 (note 1) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 (note 2) md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected external op-amp connection mode bit w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 0 0 : anex0 and anex1 are not used(note 3) 0 1 : anex0 input is a-d converted(note 4) 1 0 : anex1 input is a-d converted(note 5) 1 1 : external op-amp connection mode(note 6) b7 b6 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. frequency select bit 1 (note 2) 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 3: set "0" to psl3_5 and psl3_6 of the function select register b3. note 4: set "1" to psl3_5 of the function select register b3. note 5: set "1" to psl3_6 of the function select register b3. note 6: set "1" to psl3_5 and psl3_6 of the function select register b3. a aa a aa a a aa aa a aa a aa a aa a a aa aa a aa a aa a a aa aa a a aa aa a aa a aa a aa a aa aa aa a a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 165 figure 1.21.3. a-d converter-related registers (2) a-d control register 2 (note) symbol address when reset adcon2 0394 16 xxxxxxx0 2 b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 : without sample and hold 1 : with sample and hold bit symbol bit name function r w note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. a a a a nothing is assigned. when write, set "0". when read, their content is "0". a-d register i symbol address when reset adi(i=0 to 7) 0380 16 to 038f 16 indeterminate eight low-order bits of a-d conversion result function r w (b15) b7 b7 b0 b0 (b8) during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. when write, set "0". when read, their content is "0". during 8-bit mode when read, the content is indeterminate a a a a smp reserved bit always set to 0 a a a a 000
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 166 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conver- sion. table 1.21.2 shows the specifications of one-shot mode. figure 1.21.4 shows the a-d control regis- ter in one-shot mode. table 1.21.2. one-shot mode specifications a-d control register 0 (note 1) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w r 0 0 a-d control register 1 (note) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected external op-amp connection mode bit w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 0 : one-shot mode (note 2) b4 b3 ch0 b7 b6 1 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a aa a a aa aa a aa a aa aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a frequency select bit 1 (note 2) 0 0 : anex0 and anex1 are not used(note 3) 0 1 : anex0 input is a-d converted(note 4) 1 0 : anex1 input is a-d converted(note 5) 1 1 : external op-amp connection mode(note 6) note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 3: set "0" to psl3_5 and psl3_6 of the function select register b3. note 4: set "1" to psl3_5 of the function select register b3. note 5: set "1" to psl3_6 of the function select register b3. note 6: set "1" to psl3_5 and psl3_6 of the function select register b3. item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure 1.21.4. a-d conversion register in one-shot mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 167 (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table 1.21.3 shows the specifications of repeat mode. figure 1.21.5 shows the a-d control register in repeat mode. a-d control register 0 (note 1) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit w r 01 invalid in repeat mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected (note 2) b2 b1 b0 0 1 : repeat mode (note 2) b4 b3 b7 b6 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a frequency select bit 1 (note 2) 0 0 : anex0 and anex1 are not used(note 3) 0 1 : anex0 input is a-d converted(note 4) 1 0 : anex1 input is a-d converted(note 5) 1 1 : external op-amp connection mode(note 6) note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 3: set "0" to psl3_5 and psl3_6 of the function select register b3. note 4: set "1" to psl3_5 of the function select register b3. note 5: set "1" to psl3_6 of the function select register b3. note 6: set "1" to psl3_5 and psl3_6 of the function select register b3. note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: when changing a-d operation mode, set analog input pin again. figure 1.21.5. a-d conversion register in repeat mode item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin table 1.21.3. repeat mode specifications
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 168 (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table 1.21.4 shows the specifications of single sweep mode. figure 1.21.6 shows the a-d control register in single sweep mode. table 1.21.4. single sweep mode specifications figure 1.21.6. a-d conversion register in single sweep mode a-d control register 0 (note) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 0 invalid in single sweep mode 0 note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ?1?nor ?0?can be selected with the external op-amp connection mode bit. note 3: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 4: set "0" to psl3_5 and psl3_6 of the function select register b3. note 5: set "1" to psl3_5 of the function select register b3. note 6: set "1" to psl3_6 of the function select register b3. note 7: set "1" to psl3_5 and psl3_6 of the function select re g ister b3. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 aa a aa a aa a aa aa a a aa aa a a aa a aa a aa a aa a aa aa a a aa aa a a aa a aa a aa aa a a aa a aa a frequency select bit 1 (note 3) 0 0 : anex0 and anex1 are not used(note 4) 0 1 : anex0 input is a-d converted(note 5) 1 0 : anex1 input is a-d converted(note 6) 1 1 : external op-amp connection mode(note 7) item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ? end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ? writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 169 (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table 1.21.5 shows the specifications of repeat sweep mode 0. figure 1.21.7 shows the a-d control register in repeat sweep mode 0. figure 1.21.7. a-d conversion register in repeat sweep mode 0 a-d control register 0 (note) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 0 : any mode other than repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 0 0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 b7 b6 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a a a a a a a a a a a a a a a a a a a a aa a aa a aa a a a a a a a a a aa a frequency select bit 1 (note 3) note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ?01? nor ?10? can be selected with the external op-amp connection mode bit. note 3: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 4: set "0" to psl3_5 and psl3_6 of the function select register b3. note 5: set "1" to psl3_5 of the function select register b3. note 6: set "1" to psl3_6 of the function select register b3. note 7: set "1" to psl3_5 and psl3_6 of the function select re g ister b3. 0 0 : anex0 and anex1 are not used(note 4) 0 1 : anex0 input is a-d converted(note 5) 1 0 : anex1 input is a-d converted(note 6) 1 1 : external op-amp connection mode(note 7) item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an 0 to an3 (4 pins), an 0 to an5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) table 1.21.5. repeat sweep mode 0 specifications
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 170 item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected an 0 an 1 an 0 an 2 an 0 an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an2 (3 pins), an 0 to an3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table 1.21.6 shows the specifications of repeat sweep mode 1. figure 1.21.8 shows the a-d control register in repeat sweep mode 1. a-d control register 0 (note) symbol address when reset adcon0 0396 16 00000xxx 2 b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 bit symbol bit name function ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 trigger select bit 0 : software trigger 1 : ad trg trigger trg adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note 1) symbol address when reset adcon1 0397 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut opa0 vref connect bit 1 : repeat sweep mode 1 opa1 a-d operation mode select bit 1 1 : vref connected external op-amp connection mode bit (note 2) w r 1 1 invalid in repeat sweep mode 1 1 b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 b7 b6 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 a aa a a aa aa a aa a aa a aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a a aa aa a a aa aa frequency select bit 1 (note 3) note 1: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. note 2: neither ?01? nor ?10? can be selected with the external op-amp connection mode bit. note 3: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. note 4: set "0" to psl3_5 and psl3_6 of the function select register b3. note 5: set "1" to psl3_5 of the function select register b3. note 6: set "1" to psl3_6 of the function select register b3. note 7: set "1" to psl3_5 and psl3_6 of the function select register b3. 0 0 : anex0 and anex1 are not used(note 4) 0 1 : anex0 input is a-d converted(note 5) 1 0 : anex1 input is a-d converted(note 6) 1 1 : external op-amp connection mode(note 7) figure 1.21.8. a-d conversion register in repeat sweep mode 1 table 1.21.6. repeat sweep mode 1 specifications
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer a-d converter 171 (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 0394 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, a 28 f ad cycle is achieved with 8-bit resolution and 33 f ad with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used. (b) extended analog input pins in one-shot mode and repeat mode, the input via the extended analog input pins anex 0 and anex 1 can also be converted from analog to digital. when bit 6 of the a-d control register 1 (address 0397 16 ) is 1 and bit 7 is 0, input via anex 0 is converted from analog to digital. the result of conversion is stored in a-d register 0. when bit 6 of the a-d control register 1 (address 0397 16 ) is 0 and bit 7 is 1, input via anex 1 is converted from analog to digital. the result of conversion is stored in a-d register 1. set the related input peripheral function of the function select register b3 to disabled. (c) external operation amp connection mode in this mode, multiple external analog inputs via the extended analog input pins, anex 0 and anex 1 , can be amplified together by just one operation amp and used as the input for a-d conversion. when bit 6 of the a-d control register 1 (address 0397 16 ) is 1 and bit 7 is 1, input via an 0 to an 7 is output from anex 0 . the input from anex 1 is converted from analog to digital and the result stored in the corresponding a-d register. the speed of a-d conversion depends on the response of the external op- eration amp. do not connect the anex 0 and anex 1 pins directly. figure 1.21.9 is an example of how to connect the pins in external operation amp mode. set the related input peripheral function of the function select register b3 to disabled. analog input external o p -am p an 0 an 7 an 1 an 2 an 3 an 4 an 5 an 6 anex1 anex0 resistance ladder successive conversion register comparator figure 1.21.9. example of external op-amp connection mode
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer d-a converter 172 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. set the function select register a to i/o port, the related input peripheral function of the function select register b3 to disabled and the direction register to input mode. do not set the target port to output mode if d-a conver- sion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = vref x n/ 256 (n = 0 to 255) vref : reference voltage table 1.22.1 lists the performance of the d-a converter. figure 1.22.1 shows the block diagram of the d-a converter. figure 1.22.2 shows the d-a control register. item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels table 1.22.1. performance of d-a converter d-a register i (8) (i = 0, 1) r-2r resistance ladder (address 0398 16 , 039a 16 ) d-ai output enable bit (i = 0, 1) a aaaaaa aaaaaa p9 3 / da 0 aaaaaa aaaaaa p9 4 / da 1 data bus low-order bits figure 1.22.1. block diagram of d-a converter
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer d-a converter 173 figure 1.22.3. d-a converter equivalent circuit v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r d-a0 output enable bit da0 "1" "0" msb lsb d-a register 0 "0" "1" note 1: in the above figure, the d-a register value is "2a 16 ". note 2: this circuit is the same in d-a1. note 3: to save power when not using the d-a converter, set the d-a output enable bit to "0" and the d-a register to "00 16 ", and prevent current flowing to the r-2r resistance. figure 1.22.2. d-a control register d-a control register symbol address when reset dacon 039c 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. when write, set "0". when read, the value of these bits is "0". d-a register symbol address when reset dai (i = 0,1) 0398 16 , 039a 16 indeterminate w r b7 b0 function r w output value of d-a conversion aa a aa a aa a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer crc 174 crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is com- pleted in two machine cycles. figure 1.23.1 shows the block diagram of the crc circuit. figure 1.23.2 shows the crc-related registers. figure 1.23.2. crc-related registers symbol address when reset crcd 037d 16 , 037c 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 037e 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16 a a a a aaaaaa eight low-order bits aaaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crc data register (16) crc input register (8) aaaaaaaaaa aaaaaaaaaa crc code generating circuit x 16 + x 12 + x 5 + 1 (addresses 037d 16 , 037c 16 ) (address 037e 16 ) figure 1.23.1. block diagram of crc circuit
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer crc 175 b15 b0 (1) setting 0000 16 crc data register crcd [037d 16 , 037c 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [037e 16 ] 2 cycles after crc calculation is complete crc data register crcd [037d 16 , 037c 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [037e 16 ] after crc calculation is complete crc data register crcd [037d 16 , 037c 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1 figure 1.23.3. crc example
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer x-y converter 176 x-y converter x-y conversion rotates the 16 x 16 matrix data by 90 degrees. it can also be used to invert the top and bottom of the 16-bit data. figure 1.24.1 shows the xy control register. the xi and the yi registers are 16-bit registers. there are 16 of each (where i= 0 to 15). the xi and yi registers are mapped to the same address. the xi register is a write-only register, while the yi register is a read-only register. be sure to access the xi and yi registers in 16-bit units from an even address. operation cannot be guaranteed if you attempt to access these registers in 8-bit units. figure 1.24.1. xy control register xy control register symbol address when reset xyc 02e0 16 xxxxxx00 2 b7 b6 b5 b4 b3 b2 b1 b0 read-mode set bit xyc0 bit symbol bit name function r w 0 : data conversion 1 : no data conversion write-mode set bit 0 : no bit mapping conversion 1 : bit mapping conversion xyc1 nothing is assigned. when write, set "0". when read, the value of these bits is indeterminate. a a aa aa a a aa aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer x-y converter 177 figure 1.24.2. conversion table when the read mode set bit = 0 the reading of the yi register is controlled by the read-mode set bit (bit 0 at address 02e0 16 ). when the read-mode set bit (bit 0 at address 02e0 16 ) is 0, specific bits in the xi register can be read at the same time as the yi register is read. for example, when you read the y0 register, bit 0 bit 0 is read as bit 0 of the x0 register, bit 1 is read as bit 0 of the x1 register, ..., bit 14 is read as bit 0 of the x14 register, bit 15 as bit 0 of the x15 register. similarly, when you read the y15 register, bit 0 is bit 15 of the x0 register, bit 1 is bit 15 of the x1 register, ..., bit 14 is bit 15 of the x14 register, bit 15 is bit 15 of the x15 register. figure 1.24.2 shows the conversion table when the read mode set bit = 0. figure 1.24.3 shows the x-y conversion example. x0 register (0002c0 16 ) x1 register (0002c2 16 ) x2 register (0002c4 16 ) x3 register (0002c6 16 ) x4 register (0002c8 16 ) x5 register (0002ca 16 ) x6 register (0002cc 16 ) x7 register (0002ce 16 ) x8 register (0002d0 16 ) x9 register (0002d2 16 ) x10 register (0002d4 16 ) x11 register (0002d6 16 ) x12 register (0002d8 16 ) x13 register (0002da 16 ) x14 register (0002dc 16 ) x15 register (0002de 16 ) bit of xi register b0 b15 b0 b15 bit of yi register y0 register (0002c0 16 ) y1 register (0002c2 16 ) y2 register (0002c4 16 ) y3 register (0002c6 16 ) y4 register (0002c8 16 ) y5 register (0002ca 16 ) y6 register (0002cc 16 ) y7 register (0002ce 16 ) y8 register (0002d0 16 ) y9 register (0002d2 16 ) y10 register (0002d4 16 ) y11 register (0002d6 16 ) y12 register (0002d8 16 ) y13 register (0002da 16 ) y14 register (0002dc 16 ) y15 register (0002de 16 ) write address read address aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa x0-reg x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 x13 x14 x15 b0 b1 b2 b3 b4 b 5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 (x register) y0-reg y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 a a aa aa a a aa aa a a a a aa aa aa aa aa aa aa aa aa a a a a a a aa aa a aa aa a aa (y register) figure 1.24.3. x-y conversion example
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer x-y converter 178 figure 1.24.4. conversion table when the read mode set bit = 1 when the read-mode set bit (bit 0 at address 02e0 16 ) is 1, you can read the value written to the xi register by reading the yi register. figure 1.24.4 shows the conversion table when the read mode set bit = 1. x0,y0 register (0002c0 16 ) x1,y1 register (0002c2 16 ) x2,y2 register (0002c4 16 ) x3,y3 register (0002c6 16 ) x4,y4 register (0002c8 16 ) x5,y5 register (0002ca 16 ) x6,y6 register (0002cc 16 ) x7,y7 register (0002ce 16 ) x8,y8 register (0002d0 16 ) x9,y9 register (0002d2 16 ) x10,y10 register (0002d4 16 ) x11,y11 register (0002d6 16 ) x12,y12 register (0002d8 16 ) x13,y13 register (0002da 16 ) x14,y14 register (0002dc 16 ) x15,y15 register (0002de 16 ) b0 b15 a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa a a a a a a a a a a a a a a a a a a a a a a aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa aa bit of xi register bit of yi register write address read address the value written to the xi register is controlled by the write mode set bit (bit 1 at address 02e0 16 ). when the write mode set bit (bit 1 at address 02e0 16 ) is 0 and data is written to the xi register, the bit stream is written directly. when the write mode set bit (bit 1 at address 02e0 16 ) is 1 and data is written to the xi register, the bit sequence is reversed so that the high becomes low and vice versa. figure 1.24.5 shows the conversion table when the write mode set bit = 1. figure 1.24.5. conversion table when the write mode set bit = 1 b15 b0 b15 b0 bit of xi register write address
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 179 dram controller there is a built in dram controller to which it is possible to connect between 512 kbytes and 8 mbytes of dram. table 1.25.1 shows the functions of the dram controller. table 1.25.1 dram controller functions dram space 512kb, 1mb, 2mb, 4mb, 8mb bus control 2cas/1w refresh ________ ________ cas before ras refresh self refresh-compatible function modes edo-compatible, fast page mode-compatible waits 1 wait or 2 waits, programmable to use the dram controller, use the dram space select bit of the dram control register (address 0040 16 ) to specify the dram size. figure 1.25.1 shows the dram control register. the dram controller cannot be used in external memory mode 3 (bits 1 and 2 at address 0005 16 are 11 2 ). always use the dram controller in external memory modes 0, 1, or 2. when the data bus width is 16-bit in dram area, set "1" to r/w mode select bit (bit 2 at address 0004 16 ). set wait time between after dram power on and before memory processing, and dummy cycle for reflesh by sowtwear. dram control register symbol address when reset dramcont 00040 16 indeterminate (note 4) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 ar1 wt ar0 ar2 0 0 0 : dram ignored 0 0 1 : inhibit 0 1 0 : 0.5mb 0 1 1 : 1mb 1 0 0 : 2mb 1 0 1 : 4mb 1 1 0 : 8mb 1 1 1 : inhibit b3 b2 b1 dram space select bit wait select bit (note 1) self-refresh mode bit (note 2) sref 0 : two wait 1 : one wait 0: self-refresh off 1: self-refresh on nothing is assigned. when write, set "0". when read, the value of these bits is indeterminate. note 1: the number of cycles with 2 waits is 3-2-2. with 1 wait, it is 2-1-1. note 2: when you set "1", both ras and cas change to "l". when you set "0", ras and cas change to "h" and then normal operation (read/write, refresh) is resumed. in stop mode, there is no control. note 3: set the bus width using the external data bus width control register (address 0005 16 ). when selecting 8-bit bus width, cash is indeterminate. note 4: after reset, the content of this register is indeterminate. dram controller begins executing after writing to this register. figure 1.25.1. dram control register
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 180 ? dram controller multiplex address output the dram controller outputs the row addresses and column addresses as a multiplexed signal to the address bus a8 to a20. figure 1.25.2 shows the output format for multiplexed addresses. a9 (a20) (a19) a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) (a22) a8 a7 a6 a5 a4 a3 a2 a1 8-bit bus mode (a9) (a20) (a19) (a18) (a17) (a16) (a15) (a14) (a13) (a12) (a11) (a10) 512kb, 1mb 2mb, 4mb 8mb ma1 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 a9 (a20) a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a19 a20 a21 a9 a18 a17 a16 a15 a14 a13 a12 a11 a10 a0 (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a21 a22 a20 (a9) (a20) (a19) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) (a22) (a20) a8 a7 a6 a5 a4 a3 a2 a1 16-bit bus mode (a9) (a20) (a19) (a18) (a17) (a16) (a15) (a14) (a13) (a12) (a11) (a10) pin function 512kb 1mb, 2mb 4mb, 8mb (note 2) ma1 ma12 ma11 ma10 ma9 ma8 ma7 ma6 ma5 ma4 ma3 ma2 (a9) (a20) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) (a22) a8 a7 a6 a5 a4 a3 a2 a1 a19 a9 a9 a20 (a9) a18 a17 a16 a15 a14 a13 a12 a11 a10 (a0) a8 a7 a6 a5 a4 a3 a2 a1 row address a19 a9 a21 a20 a22 note 1: ( ) invalid bit: bits that change according to selected mode (8-bit/16-bit bus mode, dram space). note 2: the figure is for 4mx1 or 4mx4 memory configuration. if you are using a 4mx16 configuration, use combinations of the following: for row addresses, ma0 to ma12; for column addresses ma2 to ma8, ma11, and ma12. or for row addresses ma1 to ma12; for column addresses ma2 to ma9, ma11, ma12. (a8) (a8) (a8) ma0 (a8) (a8) (a8) (a8) (a8) (a8) (a8) ma0 (a8) (a8) (a8) (a8) row address row address pin function row address row address row address column address column address column address column address column address column address figure 1.25.2. output format for multiplexed addresses
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 181 figure 1.25.3. dram refresh interval set register ? refresh _______ _______ the refresh method is cas before ras. the refresh interval is set by the dram refresh interval set register (address 0041 16 ). the refresh signal is not output in hold state. figure 1.25.3 shows the dram refresh interval set register. use the following formula to determine the value to set in the refresh interval set register. refresh interval set register value = refresh interval time / (bclk frequency x 32) - 1 (0 to 255) dram refresh interval set register symbol address when reset refcnt 00041 16 indeterminate w r b7 b6 b5 b4 b3 b2 b1 b0 refresh interval set bit 0 0 0 0 0 0 0 0 : 1.6 s 0 0 0 0 0 0 0 1 : 3.2 s 0 0 0 0 0 0 1 0 : 4.8 s 1 1 1 1 1 1 1 1 : 409.6 s b7 b6 b5 b4 b3 b2 b1 b0 (note) note: refresh interval at 20 mhz operating (no division) refresh interval = bclk frequency x (refresh interval set bit + 1) x 32 refcnt0 refcnt1 refcnt2 refcnt3 refcnt4 refcnt5 refcnt6 refcnt7 bit name function bit symbol
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 182 the dram self-refresh operates in stop mode, etc. when shifting to self-refresh, select dram ignored by the dram space select bit. in the next instruction, simultaneously set the dram space select bit and self-refresh on by self-refresh mode bit. also, insert two nops after the instruction that sets the self-refresh mode bit to "1". do not access external memory while operating in self-refresh. (all external memory space access is inhibited. ) when disabling self-refresh, simultaneously select dram ignored by the dram space select bit and self- refresh off by self-refresh mode bit. in the next instruction, set the dram space select bit. do not access the dram space immediately after setting the dram space select bit. example) one wait is selected by the wait select bit and 4mb is selected by the dram space select bit shifting to self-refresh ??? mov.b #00000001b,dramcont ;dram ignored, one wait is selected mov.b #10001011b,dramcont ;set self-refresh, select 4mb and one wait nop ;two nops are needed nop ; ??? disable self-refresh ??? mov.b #00000001b,dramcont ;disable self-refresh, dram ignored, one wait is ;selected mov.b #00001011b,dramcont ;select 4mb and one wait nop ;inhibit instruction to access dram area nop ??? figures 1.25.4 to 1.25.6 show the bus timing during dram access.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 183 figure 1.25.4. the bus timing during dram access (1) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 (edo mode) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 'h' < read cycle (wait control bit = 0) > < write cycle (wait control bit = 0) > row address row address note : only casl is operating in 8-bit data bus width. note : only casl is operating in 8-bit data bus width. column address 1 column address 2 column address 3 column address 1 column address 2 column address 3
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 184 figure 1.25.5. the bus timing during dram access (2) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 (edo mode) bclk ma0 to ma12 ras cash casl dw d 0 to d 15 < read cycle (wait control bit = 1) > < write cycle (wait control bit = 1) > row address row address 'h' note : only casl is operating in 8-bit data bus width. note : only casl is operating in 8-bit data bus width. column address 1 column address 2 column address 3 column address 4 column address 1 column address 2 column address 3 column address 4
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer dram controller 185 figure 1.25.6. the bus timing during dram access (3) bclk ras cash casl bclk ras < self refresh cycle > note : only casl is operating in 8-bit data bus width. "h" dw < cas before ras refresh cycle > cash casl "h" dw note : only casl is operating in 8-bit data bus width.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 186 programmable i/o ports there are 123 programmable i/o ports: p0 to p15 (excluding p8 5 ). each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p8 5 is an input-only port and has no built-in pull-up resistance. figures 1.26.1 to 1.26.3 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), set the corresponding function select registers a, b and c. when pins are to be used as the outputs for the d-a converter, set the function select register of each pin to i/o port, and set the direction registers to input mode. table 1.26.1 lists each port and peripheral function. see the descriptions of the respective functions for how to set up the built-in peripheral devices. (1) direction registers figures 1.26.4 and 1.26.5 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding direction register for setting of bus control such as address bus and data bus is not changed. note: there is no direction register bit for p8 5 . (2) port registers figures 1.26.6 and 1.26.7 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. in memory expansion and microprocessor mode, the contents of corresponding port register for setting of bus control such as address bus and data bus is not changed. (3) function select register a figures 1.26.8 and 1.26.9 show the function select registers a. the register is used to select port output and peripheral function output when the port functions for both port output and peripheral function output. each bit of this register corresponds to each pin that functions for both port output and peripheral function output.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 187 (4) function select register b figures 1.26.10 and 1.26.11 show the function select registers b. this register selects the 1st peripheral function output and second peripheral function output when mul- tiple peripheral function outputs are assigned to a pin. for pins with a third peripheral function, this regis- ter selects whether to enable the function select register c, or output the second peripheral function. each bit of this register corresponds to each pin that has multiple peripheral function outputs assigned to it. this register is enabled when the bits of the corresponding function select register a are set for peripheral functions. the bit 3 to bit 6 of function select register b3 is ignored bit for input peripheral function. when using da0/ da1 and anex0/anex1, set related bit to "1". when not using da0/da1 or anex0/anex1, set related bit to "0". (5) function select register c figure 1.26.12 shows the function select register c. this register is used to select the first peripheral function output and the third peripheral function output when three peripheral function outputs are assigned to a pin. this register is effective when the bits of the function select register a of the counterpart pin have selected a peripheral function and when the function select register b has made effective the function select register c. the bit 7 (psc_7) is assigned the key-in interrupt inhibit bit. setting 1 in the key-in interrupt inhibit bit causes no key-in interrupts regardless of the settings in the interrupt control register even if l is entered in pins ki0 to ki3. with 1 set in the key-in interrupt inhibit bit, input from a port pin cannot be effected even if the port direction register is set to input mode. (6) pull-up control registers figures 1.26.13 and 1.26.14 show the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull-up resistance presence to the usable port as i/o port by setting. (7) port control register figure 1.26.15 shows the port control register. this register is used to choose whether to make port p1 a cmos port or an nch open drain. in the nch open drain, the port p1 has no function that a complete open drain but keeps the cmos ports pch always turned off. thus the absolute maximum rating of the input voltage falls within the range from - 0.3 v to + 0.3 v. the port control register functions similarly to the above also in the case in which port p1 can be used as a port when the bus width in the full external areas comprises 8 bits in either microprocessor mode or in memory expansion mode.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 188 figure 1.26.1. programmable i/o ports (1) p0 0 to p0 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 7 , p5 0 to p5 2 , p5 4 to p5 7 , p11 0 to p11 4 , p12 0 to p12 7 , p13 0 to p13 7 , p14 0 to p14 6 , p15 0 to p15 7 p1 0 to p1 4 p1 5 to p1 7 p6 2 , p6 6 , p7 7 , p8 7 data bus direction register pull-up selection pull-up selection pull-up selection pull-up selection direction register port latch port p1 control register bit 0 direction register port latch port latch port latch direction register port p1 control register bit 0 data bus data bus data bus input to respective peripheral functions input to respective peripheral functions
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 189 p8 5 aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaaaa aa aa aa a note function select register a port latch pull-up selection p8 2 to p8 4 p6 0 , p6 1 , p6 4 , p6 5 , p7 2 , p7 3 p7 5 , p8 1 , p9 0 , p9 1 , p9 2 , p9 7 (inside dotted-line not included) p5 3 , p6 3 , p6 7 , p7 4 , p7 6 , p8 0 , p8 6 (inside dotted-line included) note : p5 3 is connected to clock output function select bit. p7 0 , p7 1 direction register input to respective peripheral functions direction register direction register port latch port latch pull-up selection input to respective peripheral functions input to respective peripheral functions function select register a data bus data bus data bus data bus output from respective peripheral functions output from respective peripheral functions nmi interrupt input figure 1.26.2. programmable i/o ports (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 190 figure 1.26.3. programmable i/o ports (3) p10 0 to p10 3 p9 3 , p9 4 d-a output enabled p9 5 (inside dotted-line included) p9 6 (inside dotted-line not included) aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aaaaaaaaaaaaaaaaaaa aa aa aa a p10 4 to p10 7 port latch pull-up selection direction register input to respective peripheral functions data bus port latch direction register port latch direction register port latch direction register pull-up selection pull-up selection pull-up selection data bus data bus data bus input to respective peripheral functions input to respective peripheral functions analog input analog input analog input analog input function select register a function select register a output from respective peripheral functions output from respective peripheral functions
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 191 figure 1.26.4. direction register (1) symbol address when reset pdi (i = 0 to 15, 03e2 16 , 03e3 16 , 03e6 16 , 03e7 16 , 03ea 16 00 16 except 8, 11, 14) 03eb 16 , 03c2 16 , 03c3 16 , 03c7 16 , 03ca 16 00 16 03ce 16 , 03cf 16 , 03d3 16 00 16 port pi direction register (note 1,2) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 direction register pdi_1 port pi 1 direction register pdi_2 port pi 2 direction register pdi_3 port pi 3 direction register pdi_4 port pi 4 direction register pdi_5 port pi 5 direction register pdi_6 port pi 6 direction register pdi_7 port pi 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) (i = 0 to 15 except 8, 11, 14) port p8 direction register symbol address when reset pd8 03c6 16 00x00000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p8 0 direction register pd8_1 port p8 1 direction register pd8_2 port p8 2 direction register pd8_3 port p8 3 direction register pd8_4 port p8 4 direction register nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. pd8_6 port p8 6 direction register pd8_7 port p8 7 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) note 1: set bit 2 of protect register (address 000a 16 ) to ??before rewriting to the port p9 direction register. note 2: in memory expansion and microprocessor mode, the contents of corresponding port pi direction register for setting of bus control such as address bus and data bus is not changed. a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 192 port p11 direction register symbol address when reset pd11 03cb 16 , xxx00000 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd11_0 port p11 0 direction register pd11_1 port p11 1 direction register pd11_2 port p11 2 direction register pd11_3 port p11 3 direction register pd11_4 port p11 4 direction register 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) port p14 direction register symbol address when reset pd14 03d2 16 x0000000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd14_0 port p14 0 direction register pd14_1 port p14 1 direction register pd14_2 port p14 2 direction register pd14_3 port p14 3 direction register pd14_4 port p14 4 direction register nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. 0 : input mode (functions as an input port) 1 : output mode (functions as an output port) a a aa aa a aa a aa a aa a aa a aa a aa a aa a aa a aa a aa nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. pd14_5 port p14 5 direction register pd14_6 port p14 6 direction register a a aa aa figure 1.26.5. direction register (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 193 figure 1.26.6. port register (1) symbol address when reset pi (i = 0 to 15, 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate except 8, 11, 14) 03e9 16 , 03c0 16 , 03c1 16 , 03c5 16 , 03c8 16 indeterminate 03cc 16 , 03cd 16 , 03d1 16 indeterminate port pi register (note 1) bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pdi_0 port pi 0 register pdi_1 port pi 1 register pdi_2 port pi 2 register pdi_3 port pi 3 register pdi_4 port pi 4 register pdi_5 port pi 5 register pdi_6 port pi 6 register pdi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (note 2) (i = 0 to 15 except 8, 11, 14) port p8 register symbol address when reset p8 03c4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pd8_0 port p80 register pd8_1 port p81 register pd8_2 port p82 register pd8_3 port p83 register pd8_4 port p84 register pd8_5 port p85 register pd8_6 port p86 register pd8_7 port p87 register data is input and output to and from each pin by reading and writing to and from each corresponding bit (except for p8 5 ) 0 : ??level data 1 : ??level data a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a a note 1: in memory expansion and microprocessor mode, the contents of corresponding port pi direction register for setting of bus control such as address bus and data bus is not changed. note 2: p7 0 and p7 1 are n-channel open drain ports and high inpedance outputs.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 194 port p11 register symbol address when reset p11 03c9 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p11_0 port p11 0 register p11_1 port p11 1 register p11_2 port p11 2 register p11_3 port p11 3 register p11_4 port p11 4 register port p14 register symbol address when reset p14 03d0 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 p14_0 port p14 0 register p14_1 port p14 1 register p14_2 port p14 2 register p14_3 port p14 3 register p14_4 port p14 4 register nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. a a a a a a a a a a a a a a a a a a a a a a a a nothing is assigned. this bit can either be set nor reset. when read, its content is indeterminate. p14_5 port p14 5 register p14_6 port p14 6 register a a a a data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : l level data 1 : h level data figure 1.26.7. port register (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 195 p6 0 p6 1 p6 2 p6 3 p6 4 p6 5 p6 6 p6 7 p7 0 p7 1 p7 2 p7 3 p7 4 p7 5 p7 6 p7 7 p8 0 p8 1 p8 2 p8 3 p8 4 p8 5 p8 6 p8 7 p9 0 p9 1 p9 2 p9 3 p9 4 p9 5 p9 6 p9 7 clk 0 output t x d 0 output clk 1 output t x d 1 output t x d 2 (sda 2) output scl 2 output clk 2 output ta2 out output ta3 out output ta4 out output clk 3 output scl 3 output t x d 3 (sda 3) output clk 4 output t x d 4 (sda 4) output scl 3 output port periphral output function 1 periphraloutput function 2 periphral output function 3 clks 1 output ta0 out output ta1 out output w phase output u phase output v phase output rts 0 output rts 1 output rts 2 output w phase output u phase output rts 3 output rts 4 output v phase output st x d 4 output st x d 3 output table 1.26.1. each port and peripheral function (note 1) note 1: when using peripheral input function, set the corresponding function select register a to "0" (i/o port). note 2: n-channel open drain output. (note 2) (note 2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 196 figure 1.26.8. function select register a (1) function select register a0 symbol address when reset ps0 03b0 16 0x000x00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 port p6 0 function select bit ps0_0 0 : i/o port 1 : rts0 output port p6 1 function select bit ps0_1 0 : i/o port 1 : clk0 output port p6 3 function select bit ps0_3 0 : i/o port 1 : txd0 output port p6 4 function select bit ps0_4 0 : i/o port 1 : peripheral function output (psl0_4 enabled) port p6 5 function select bit ps0_5 0 : i/o port 1 : clk1 output port p6 7 function select bit ps0_7 0 : i/o port 1 : txd1 output function select register a1 symbol address when reset ps1 03b1 16 x0000000 2 w r b7 b6 b5 b4 b3 b2 b1 b0 port p7 0 function select bit (note) ps1_0 0 : i/o port 1 : peripheral function output (psl1_0 enabled) port p7 3 function select bit ps1_3 0 : i/o port 1 : peripheral function output (psl1_3 enabled) port p7 4 function select bit ps1_4 0 : i/o port 1 : peripheral function output (psl1_4 enabled) port p7 5 function select bit ps1_5 port p7 2 function select bit ps1_2 0 : i/o port 1 : peripheral function output (psl1_2, psc_0 enabled) 0 : i/o port 1 : w phase output port p7 6 function select bit ps1_6 0 : i/o port 1 : ta3out output port p7 1 function select bit (note) ps1_1 0 : i/o port 1 : scl2 output nothing is assigned. when write, set "0". when read, the content is indeterminate. nothing is assigned. when write, set "0". when read, the content is indeterminate. nothing is assigned. when write, set "0". when read, the content is indeterminate. bit name function bit symbol a a aa aa a a aa aa a aa a aa a aa a aa a aa a aa a aa a a aa aa a aa a a aa aa a aa note: this port is n-channel open drain output.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 197 figure 1.26.9. function select register a (2) function select register a2 symbol address when reset ps2 03b4 16 xxxxxx00 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 port p8 0 function select bit ps2_0 0 : i/o port 1 : peripheral function output (psl2_0 enabled) port p8 1 function select bit ps2_1 0 : i/o port 1 : u phase output function select register a3 (note) symbol address when reset ps3 03b5 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 port p9 0 function select bit ps3_0 0 : i/o port 1 : clk3 output port p9 3 function select bit ps3_3 0 : i/o port 1 : rts3 output port p9 4 function select bit ps3_4 0 : i/o port 1 : rts4 output port p9 5 function select bit ps3_5 port p9 2 function select bit ps3_2 0 : i/o port 1 : txd 3 (sda 3 ) output 0 : i/o port 1 : clk4 output port p9 6 function select bit ps3_6 0 : i/o port 1 : txd 4 (sda 4 ) output port p9 1 function select bit ps3_1 0 : i/o port 1 : peripheral function output (psl3_1 enabled) nothing is assigned. when write, set "0". when read, the content is indeterminate. bit name function bit symbol port p9 7 function select bit ps3_7 0 : i/o port 1 : peripheral function output (psl3_7 enabled) note: set bit 2 of protect register (address 000a 16 ) to ??before rewriting to this register. a a a a a a a a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 198 figure 1.26.10. function select register b (1) function select register b0 symbol address when reset psl0 03b2 16 xxx0xxxx 2 bit name bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 port p6 4 peripheral function select bit (enabled when ps0_4 = 1) psl0_4 function select register b1 symbol address when reset psl1 03b3 16 xxx000x0 2 w r b7 b6 b5 b4 b3 b2 b1 b0 port p7 0 peripheral function select bit (enabled when ps1_0 = 1) (note 2) psl1_0 psl1_3 psl1_4 psl1_2 0 : port p7 2 peripheral subfunction select bit psc_0) is enabled 1 : ta1 out output (note 1) nothing is assigned. when write, set "0". when read, the content is indeterminate. bit name bit symbol function 0 : rts1 output 1 : clks1 output 0 : txd 2 (sda 2 ) port 1 : ta0 out output 0 : rts2 port 1 : v phase output 0 : ta2 out port 1 : w phase output function note 1: set psc_0 to ?? note 2: this port is n-channel open drain output. nothing is assigned. when write, set "0". when read, the content is indeterminate. port p7 0 peripheral function select bit (enabled when ps1_2 = 1) port p7 0 peripheral function select bit (enabled when ps1_4 = 1) port p7 0 peripheral function select bit (enabled when ps1_3 = 1) nothing is assigned. when write, set "0". when read, the content is indeterminate. nothing is assigned. when write, set "0". when read, the content is indeterminate. aa aa a a aa a aa a aa a aa a function select register b2 symbol address when reset psl2 03b6 16 xxxxxxx0 2 w r b7 b6 b5 b4 b3 b2 b1 b0 port p8 0 peripheral function select bit (enabled when ps2_0 = 1) psl2_0 bit name bit symbol 0 : ta4 out output 1 : u phase output function nothing is assigned. when write, set "0". when read, the content is indeterminate. aa a
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 199 figure 1.26.11. function select register b (2) function select register b3 symbol address when reset psl3 03b7 16 xxxxxxxx 2 b7 b6 b5 b4 b3 b2 b1 b0 w r bit name function nothing is assigned. when write, set "0". when read, the content is indeterminate. port p9 1 peripheral function select bit psl3_1 0 : scl 3 output 1 : stxd 3 output port p9 3 peripheral function psl3_3 0 : input peripheral function enabled (except da0 output) (note) 1 : input peripheral function disabled (da0 output) port p9 4 peripheral function psl3_4 port p9 5 peripheral function psl3_5 port p9 6 peripheral function psl3_6 port p9 7 peripheral function select bit psl3_7 0 : scl 4 output 1 : stxd 4 output a a a a a a a a a a a a a a nothing is assigned. when write, set "0". when read, the content is indeterminate. a a bit symbol 0 : input peripheral function enabled (except da1 output) (note) 1 : input peripheral function disabled (da1 output) 0 : input peripheral function enabled (except anex0 use) (note) 1 : input peripheral function disabled (anex0 use) 0 : input peripheral function enabled (except anex1 use) (note) 1 : input peripheral function disabled (anex1 use) note: although da0, da1 output and anex0, anex1 can be used when "0" is set in these bits, the power supply may be increased. figure 1.26.12. function select register c function select register c symbol address when reset psc 03af 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 port p7 2 peripheral subfunction select bit (enabled when ps1_2 = 1 and psl1_2 = 0) psc_0 (note 1) psc_7 (note 2) 0 : enabled 1 : disabled bit name bit symbol 0 : clk2 output 1 : v phase output function note 1: set this bit to "0" when psl1_2 = "1". note 2: when this bit is "1", key input interrupt for interrupt controller is disabled regardless of port input and setting of interrupt control register. when changing this bit, set key input interrupt disabled by key input interrupt control register. key input interrupt disable bit nothing is assigned. when write, set "0". when read, the content is indeterminate. a aa aa a a aa aa
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 200 figure 1.26.13. pull-up control register (1) pull-up control register 0 (note) symbol address when reset pur0 03f0 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu00 p0 0 to p0 3 pull-up pu01 p0 4 to p0 7 pull-up pu02 p1 0 to p1 3 pull-up pu03 p1 4 to p1 7 pull-up pu04 p2 0 to p2 3 pull-up pu05 p2 4 to p2 7 pull-up pu06 p3 0 to p3 3 pull-up pu07 p3 4 to p3 7 pull-up the corresponding port is pulled high with a pull-up resistance 0 : not pulled high 1 : pulled high aa a aa aa a a aa a aa aa a a aa a aa a aa a aa a pull-up control register 1 (note) symbol address when reset pur1 03f1 16 x0 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p4 0 to p4 3 pull-up pu11 p4 4 to p4 7 pull-up pu12 p5 0 to p5 3 pull-up pu13 p5 4 to p5 7 pull-up the corresponding port is pulled high with a pull-up resistance 0 : not pulled high 1 : pulled high note 1: since p7 0 and p7 1 are n-channel open drain ports, pull-up is not available for them. note 2: except port p8 5 . aa a aa aa a a aa a aa a pull-up control register 2 symbol address when reset pur2 03da 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu20 p8 0 to p8 3 pull-up pu21 p8 4 to p8 7 pull-up (note 2) pu22 p9 0 to p9 3 pull-up pu23 p9 4 to p9 7 pull-up the corresponding port is pulled high with a pull-up resistance 0 : not pulled high 1 : pulled high aa a aa a aa aa a a aa a nothing is assigned. theses bits can neither be set nor reset. when read, their contents are 0. pu14 p6 0 to p6 3 pull-up pu15 p6 4 to p6 7 pull-up pu16 p7 0 to p7 3 pull-up (note 1) pu17 p7 4 to p7 7 pull-up aa a aa aa a a aa a aa aa a a note: since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull- up resistance presence to the usable port as i/o port by setting. note: since p0 to p5 operate as the bus in memory expansion mode and microprocessor mode, do not set the pull-up control register. however, it is possible to select pull- up resistance presence to the usable port as i/o port by setting.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 201 figure 1.26.14. pull-up control register (2) pull-up control register 3 symbol address when reset pur3 03db 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu30 p10 0 to p10 3 pull-up pu31 p10 4 to p10 7 pull-up pu32 p11 0 to p11 3 pull-up pu33 p11 4 pull-up pu34 p12 0 to p12 3 pull-up pu35 p12 4 to p12 7 pull-up pu36 p13 0 to p13 3 pull-up pu37 p13 4 to p13 7 pull-up the corresponding port is pulled high with a pull-up resistance 0 : not pulled high 1 : pulled high aa a aa a aa aa a a aa a aa a aa aa a a aa a aa a pull-up control register 4 symbol address when reset pur4 03dc 16 xxxx0000 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu40 p14 0 to p14 3 pull-up pu41 p14 4 to p14 6 pull-up pu42 p15 0 to p15 3 pull-up pu43 p15 4 to p15 7 pull-up the corresponding port is pulled high with a pull-up resistance 0 : not pulled high 1 : pulled high aa a aa a aa a aa a nothing is assigned. theses bits can neither be set nor reset. when read, their contents are 0. figure 1.26.15. port control register port control register (note 1) symbpl address when reset pcr 03ff 16 xxxxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pcr0 port p1 control register 0 : function as common cmos port 1 : function as n-ch open drain port (note 2) nothing is assigned. when write, set "0". when read, their contents are indeterminate. a a aa aa note 1: since p1 operates as the data bus in memory expansion mode and microprocessor mode, do not set the port control register. however, it is possible to select the cmos port or n-channel open drain to the usable port as i/o port by setting. note 2: this function is designed to permanently turn off the pch of the cmos port.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer programmable i/o port 202 table 1.26.2. example connection of unused pins in single-chip mode figure 1.26.16. example connection of unused pins table 1.26.3. example connection of unused pins in memory expansion mode and microprocessor mode port p0 to p15 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc byte av ss v ref microcomputer v cc v ss in single-chip mode port p6 to p15 (except for p8 5 ) (input mode) (input mode) (output mode) nmi x out av cc av ss v ref open microcomputer v cc v ss in memory expansion mode or in microprocessor mode hold rdy ale bclk bhe hlda open open open pin name connection ports p0 to p15 (excluding p8 5 ) x out (note) av ss , v ref , byte av cc after setting for input mode, connect every pin to v ss via a resistance (pull-down); or after setting for output mode, leave these pins open. open connect to v cc connect to v ss note: with external clock input to x in pin. nmi connect via resistance to v cc (pull-up) pin name connection ports p6 to p15 (excluding p8 5 ) av ss , v ref av cc open connect to v cc connect to v ss note: with external clock input to x in pin. hold, rdy, nmi connect via resistance to v cc (pull-up) bhe, ale, hlda, x out (note), bclk after setting for input mode, connect every pin to v ss via a resistance( pull-down); or after setting for output mode, leave these pins open.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 203 usage precaution sfr (1) addresses 03c9 16 , 03cb 16 to 03d3 16 area is for future plan. must set "ff 16 " to address 03cb 16 , 03ce 16 , 03cf 16 , 03d2 16 , 03d3 16 at initial setting. timer a (timer mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 . reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. timer a (event counter mode) (1) reading the timer ai register while a count is in progress allows reading, with arbitrary timing, the value of the counter. reading the timer ai register with the reload timing gets ffff 16 by under- flow or 0000 16 by overflow. reading the timer ai register after setting a value in the timer ai register with a count halted but before the counter starts counting gets a proper value. (2) when stop counting in free run type, set timer again. timer a (one-shot timer mode) (1) setting the count start flag to 0 while a count is in progress causes as follows: ? the counter stops counting and a content of reload register is reloaded. ? the tai out pin outputs l level. ? the interrupt request generated and the timer ai interrupt request bit goes to 1. (2) the timer ai interrupt request bit goes to 1 if the timer's operation mode is set using any of the following procedures: ? selecting one-shot timer mode after reset. ? changing operation mode from timer mode to one-shot timer mode. ? changing operation mode from event counter mode to one-shot timer mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. timer a (pulse width modulation mode) (1) the timer ai interrupt request bit becomes 1 if setting operation mode of the timer in compliance with any of the following procedures: ? selecting pwm mode after reset. ? changing operation mode from timer mode to pwm mode. ? changing operation mode from event counter mode to pwm mode. therefore, to use timer ai interrupt (interrupt request bit), set timer ai interrupt request bit to 0 after the above listed changes have been made. (2) setting the count start flag to 0 while pwm pulses are being output causes the counter to stop counting. if the tai out pin is outputting an h level in this instance, the output level goes to l, and the timer ai interrupt request bit goes to 1. if the tai out pin is outputting an l level in this instance, the level does not change, and the timer ai interrupt request bit does not becomes 1.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 204 timer b (timer mode, event counter mode) (1) reading the timer bi register while a count is in progress allows reading , with arbitrary timing, the value of the counter. reading the timer bi register with the reload timing gets ffff 16 . reading the timer bi register after setting a value in the timer bi register with a count halted but before the counter starts counting gets a proper value. timer b (pulse period/pulse width measurement mode) (1) if changing the measurement mode select bit is set after a count is started, the timer bi interrupt request bit goes to 1. (2) when the first effective edge is input after a count is started, an indeterminate value is transferred to the reload register. at this time, timer bi interrupt request is not generated. a-d converter (1) write to each bit (except bit 6) of a-d control register 0, to each bit of a-d control register 1, and to bit 0 of a-d control register 2 when a-d conversion is stopped (before a trigger occurs). in particular, when the vref connection bit is changed from 0 to 1, start a-d conversion after an elapse of 1 m s or longer. (2) when changing a-d operation mode, select analog input pin again. (3) using one-shot mode or single sweep mode read the correspondence a-d register after confirming a-d conversion is finished. (it is known by a- d conversion interrupt request bit.) (4) using repeat mode, repeat sweep mode 0 or repeat sweep mode 1 use the undivided main clock as the internal cpu clock. (5) when f(x in ) is faster than 10 mhz, make the frequency 10 mhz or less by dividing. (6) to carry out a-d conversion properly, charging the internal capacitor c shown in figure 2.7.29 has to be completed within a specified period of time. with t as the specified time, time t is the time that switches sw2 and sw3 are connected to o in figure 2.7.28. let output impedance of sensor equiva- lent circuit be r0, microcomputers internal resistance be r, precision (error) of the a-d converter be x, and the a-d converters resolution be y (y is 1024 in the 10-bit mode, and 256 in the 8-bit mode). vc is generally v c = v in {1 C e } and when t = t, v c =v in C v in =v in (1 C ) e = C =ln hence, r0 = C C r c (r0 +r) t c (r0 + r) t C c (r0 + r) t C y x y x y x y x c ? ln t y x
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 205 with the model shown in figure 1.27.1 as an example, when the difference between v in and v c becomes 0.1lsb, we find impedance r0 when voltage between pins v c changes from 0 to v in -(0.1/1024) v in in time t. (0.1/1024) means that a-d precision drop due to insufficient capacitor charge is held to 0.1lsb at time of a-d conversion in the 10-bit mode. actual error however is the value of absolute precision added to 0.1lsb. when f(x in ) = 10 mhz, t = 0.3 us in the a-d conversion mode with sample & hold. output impedance r0 for sufficiently charging capacitor c within time t is determined as follows. t = 0.3 m s, r = 7.8 k w , c = 3 pf, x = 0.1, and y = 1024 . hence, r0 = C C7.8 x10 3 3.0 x 10 3 thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the a-d con- verter turns out to be approximately 3.0 k w . tables 1.27.1 and 1.27.2 show output impedance values based on the lsb values. 3.0 x 10 C12 ? ln 1024 0.1 0.3 x 10 -6 v c c (3.0pf) v in microprocessor's inside sensor-equivalent circuit r (7.8k ) r 0 figure 1.27.1 a circuit equivalent to the a-d conversion terminal w
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 206 tables 1.27.1. output impedance values based on the lsb values (10-bit mode) tables 1.27.2. output impedance values based on the lsb values (8-bit mode) f(xin) (mhz) cycle ( m s) sampling time ( m s) r (kohm) c (pf) resolution (lsb) r0max (kohm) 10 0.1 0.3 (3 x cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 3.0 4.5 5.3 5.9 6.4 6.8 7.2 7.5 7.8 8.1 0.4 0.9 1.3 1.7 2.0 2.2 2.4 2.6 2.8 10 0.1 0.2 (2 x cycle, sample & hold bit is enabled) 7.8 3.0 f(xin) (mhz) cycle ( m s) sampling time ( m s) r (kohm) c (pf) resolution (lsb) r0max (kohm) 10 0.1 0.3 (3 x cycle, sample & hold bit is enabled) 7.8 3.0 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 4.9 7.0 8.2 9.1 9.9 10.5 11.1 11.7 12.1 12.6 0.7 2.1 2.9 3.5 4.0 4.4 4.8 5.2 5.5 5.8 10 0.1 0.2 (2 x cycle, sample & hold bit is enabled) 7.8 3.0
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 207 stop mode and wait mode ____________ (1) when returning from stop mode by hardware reset, reset pin must be set to l level until main clock oscillation is stabilized. (2) when shifting to wait mode or stop mode, the program stops after reading from the wait instruc- tion and the instruction that sets all clock stop control bits to 1 in the instruction queue. therefore, insert a minimum of 4 nops after the wait instruction and the instruction that sets all clock stop control bits to 1 in order to flush the instruction queue. interrupts (1) setting the stack pointer ? the value of the stack pointer is initialized to 0000 16 immediately after reset. accepting an interrupt before setting a value in the stack pointer may cause runaway. be sure to set a value in the stack pointer before accepting an interrupt. _______ when using the nmi interrupt, initialize the stack pointer at the beginning of a program. regard- _______ ing the first instruction immediately after reset, generating any interrupts including the nmi inter- rupt is prohibited. set an even address to the stack pointer so that operating efficiency is increased. _______ (2) the nmi interrupt _______ ? as for the nmi interrupt pin, an interrupt cannot be prohibited. connect it to the v cc pin if unused. (3) address match interrupt do not set the following addresses to the address match interrupt register. 1. the start address of an interrupt instruction 2. address of an instruction to clear an interrupt request bit of an interrupt control register or any of the next 7 instructions addresses immediately after an instruction to rewrite an interrupt priority level to a smaller value 3. any of the next 3 instructions addresses immediately after an instruction to set the interrupt enable flag (i flag). 4. any of the next 3 instructions addresses immediately after an instruction to rewrite a processor interrupt priority level (ipl) to a smaller value. example 1) interrupt_a: ; interrupt a routine pushm r0,r1,r2,r3,a0,a1 ; <---- ???? ; example 2) mov.b #0,ta0ic ;change ta0 interrupt priority level to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction nop ; 4th instruction nop ; 5th instruction nop ; 6th instruction nop ; 7th instruction do not set address match interrupt during this period do not set address match interrupt to the start address of an interrupt instruction
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 208 example 3) fset i ; set i flag ( interrupt enabled) nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction example 4) ldipl #0 ; rewrite ipl to a smaller value nop ; 1st instruction nop ; 2nd instruction nop ; 3rd instruction dmac (1) do not clear the dma request bit of the dmai request cause select register. in m16c/80, when a dma request is generated while the channel is disabled (note), the dma transfer is not executed and the dma request bit is cleared automatically. note :the dma is disabled or the transfer count register is "0". (2) when dma transfer is done by a software trigger, set dsr and drq of the dmai request cause select register to "1" simultaneously using the or instruction. e.g.) or.b #0a0h, dmisl ; dmisl is dmai request cause select register (3) when changing the dmai request cause select bit of the dmai request cause select register, set "1" to the dma request bit, simultaneously. in this case, the corresponding dma channel is set to disabled. at least 2 instructions are needed from the instruction to write to the dmai request cause select bit to enable dma. example) when dma request cause is changed to timer a0 and using dma0 in single transfer after dma initial setting push.w r0 ; store r0 register stc dmd0, r0 ; read dma mode register 0 and.b #11111100b, r0l ; clear dma0 transfer mode select bit to "00" ldc r0, dmd0 ; dma0 disabled mov.b #10000011b, dm0sl ; select timer a0 ; (write "1" to dma request bit simultaneously) mov.b r0l, r0l ; dummy cycle or.b #00000001b, r0l ; set dma0 single transfer ldc r0, dmd0 ; dma0 enabled pop.w r0 ; restore r0 register noise (1) a bypass capacitor should be inserted between vcc-vss line for reducing noise and latch-up connect a bypass capacitor (approx. 0.1 m f) between the vcc and vss pins using short wiring and thicker circuit traces. at least 2 instructions are needed until dma enabled. do not set address match interrupt during this period do not set address match interrupt during this period
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer usage precaution 209 reducing power consumption (1) when a-d conversion is not performed, select the vref not connected with the vref connect bit of a-d control register 1. when a-d conversion is performed, start the a-d conversion at least 1 m s or longer after connecting vref. (2) when using an4 (p10 4 ) to an7 (p10 7 ), select the input disable of the key input interrupt signal with the key input interrupt disable bit of the function select register c . when selecting the input disable of the key input interrupt signal, the key input interrupt cannot be used. also, the port cannot be input even if the direction register of p10 4 to p10 7 is set to input (the input result becomes undefined). when the input disable of the key input interrupt signal is selected, use all an4 to an7 as a-d inputs. (3) when anex0 and anex1 are used, select the input peripheral function disable with port p9 5 and p9 6 input peripheral function select bit of the function select register b3. when the input peripheral function disable is selected, the port cannot be input even if the port direc- tion register is set to input (the input result becomes undefined). also, it is not possible to input a peripheral function except anex0 and anex1. (4) when d-a converter is not used, set output disabled with the d-a output enable bit of d-a control register and set the d-a register to "00 16 ". (5) when d-a conversion is used, select the input peripheral function disabled with port p9 3 and p9 4 input peripheral function select bit of the function select register b3. when the input peripheral function disabled is selected, the port cannot be input even if the port direction register is set to input (the input result becomes undefined). also, it is not possible to input a peripheral function. precautions for using clk out pin when using the clock output function of p5 3 /clk out pin (f 8 , f 32 or fc output) in single chip mode, use port p5 7 as an input only port (port p5 7 direction register is "0"). although port p5 7 may be set as an output port, it will become high impedance and will not output "h" or "l" levels. external rom version the external rom version is operated only in microprocessor mode, so be sure to perform the following: ? connect cnvss pin to vcc. ? fix the processor mode bit to 11 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics 210 table 1.28.1. absolute maximum ratings note: specify a product of -40 to 85 c to use it. v ref , x in x out v o -0.3 to vcc+0.3 -0.3 to vcc+0.3 p d topr=25 -0.3 to 6.5 -0.3 to 6.5 v v v v i avcc vcc t stg t opr mw v -65 to 150 500 -20 to 85 / -40 to 85(note) p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 7 , p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 ,p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 ,p7 2 -p7 7 , p8 0 -p8 4, p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , reset, p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , p7 0 , p7 1 p7 0 , p7 1 -0.3 to 6.5 -0.3 to 6.5 v v (maskrom : cnv ss , byte), v cc =av cc v cc =av cc c c c symbol parameter condition rated value unit supply voltage analog supply voltage input voltage output voltage power dissipation operating ambient temperature storage temperature electrical characteristics
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics 211 note 1: the mean output current is the mean value within 100ms. note 2: the total i ol (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, p10, p11, p14 and p15 must be 80ma max. the total i oh (peak) for ports p0, p1, p2, p8 6 , p8 7 , p9, p10, p11, p14 and p15 must be 80ma max. the total i ol (peak) for ports p3, p4, p5, p6, p7, p8 0 to p8 4 , p12 and p13 must be 80ma max. the total i oh (peak) for ports p3, p4, p5, p6, p7 2 to p7 7 , p8 0 to p8 4 , p12 and p13 must be 80ma max. note 3: specify a product of -40 to 85 c to use it. note 4: the specification of v ih and v il of p8 7 is not when using as x cin but when using programmable input port. table 1.28.2. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at topr = C 20 to 85 o c / C 40 to 85 o c(note3) unless otherwise specified) p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , vcc vcc avcc v v 0 0 v ih i oh ( av g) ma ma vss avss 0.8vcc v v v v v v v 0.8vcc 0.5vcc vcc vcc vcc 0.2vcc 0.2vcc 0 0 0 (data input function during memory expansion and microprocessor modes) 0.16vcc i oh (p eak ) p7 2 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , -5.0 -10.0 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 (during single-chip mode) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4, p8 6, p8 7, p9 0 -p9 7, p10 0 -p10 7, p4 0 -p4 7 , p5 0 -p5 7, p6 0 -p6 7 , 10.0 5.0 ma f (x in ) mhz i ol (p eak ) ma i ol ( av g) 20 f (xc in ) khz 50 32.768 x in , reset, cnv ss , byte p7 0 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p4 0 -p4 7 , p5 0 -p5 7, p6 0 -p6 7 , x in , reset, cnv ss , byte (data input function during memory expansion and microprocessor modes) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 (during single-chip mode) p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 vcc=4.2v to 5.5v p7 0 , 0.8vcc 6.5 v p7 1 v il 0 vcc=2.7v to 5.5v 0 mhz 10 s y mbol parameter unit standard min typ. max. supply voltage analog supply voltage supply voltage analog supply voltage high input voltage low input voltage high peak output current high average output current low peak output current low average output current main clock input oscillation frequency subclock oscillation frequency no wait 2.7 5.5 5.0 v p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4, p8 6, p8 7, p9 0 -p9 7, p10 0 -p10 7, p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4, p8 6, p8 7, p9 0 -p9 7, p10 0 -p10 7, p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4, p8 6, p8 7, p9 0 -p9 7, p10 0 -p10 7, p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics (v cc = 5v) 212 table 1.28.3. electrical characteristics (referenced to v cc =5v, v ss =0v at topr=25 o c, f(x in )=20mh z unless otherwise specified) v cc = 5v v v 4.7 v x out 3.0 3.0 v 2.0 0.45 v v x out 2.0 2.0 3.0 i oh = - 5ma i oh = - 1ma i oh = - 200 m a i oh = - 0.5ma i ol =5ma i ol =1ma i ol =200 m a i ol =0.5ma highpower lowpower highpower lowpower highpower lowpower x cout 3.0 1.6 v ta0 out -ta4 out ,nmi, 0.2 1.0 v int 0 -int 5 ,ad trg , cts 0 -cts 4 , clk 0 -clk 4 , hold, rdy, ta0 in -ta4 in , tb0 in -tb5 in , v x cout 0 0 highpower lowpower ki 0 -ki 3, rxd0-rxd4, v oh v oh v oh v ol v ol v ol v t+- v t- symbol high output voltage high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage low output voltage hysteresis with no load applied with no load applied with no load applied with no load applied parameter unit standard min typ. max. measuring condition 0.2 1.8 v 5.0 2.0 v ma reset 20.0 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , x in , reset, cnvss, byte v i =5v v i =0v - 5.0 45.0 72.0 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , x in , reset, cnvss, byte 4.0 100.0 6.0 1.0 m w m w 50.0 k w p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , v i =0v 30.0 167.0 i ih i il v ram icc v t+- v t- r fxin r fxcin r pullup hysteresis high input current low input current pull-up resistance x in x cin feedback resistance feedback resistance ram retention voltage f(x in )=20mhz f(x cin )=32khz power supply current when clock is stopped in single-chip mode, the output pins are open and other pins are v ss square wave, no division square wave f(x cin )=32khz topr=85 c when clock is stopped topr=25 c when clock is stopped when a wait instruction is executed m a m a m a m a 50.0 80.0 7.0 ma p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 scl 2 -scl 4, sda 2 -sda 4 mask rom 128 kb version flash memory version mask rom 256 kb version 50.0 80.0 mask rom 128 kb version flash memory version mask rom 256 kb version 90.0 m a mask rom 128 kb version romless ram 10kb version flash memory version mask rom 256 kb version romless ram 24kb version 1.0 2.0 1.0 measuring condition:
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics (v cc = 5v) 213 table 1.28.4. a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, v ss = av ss = 0v at topr = 25 o c, f(x in ) = 20mh z unless otherwise specified) v cc = 5v m s standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc 3 10 symbol parameter measuring condition unit r ladder t conv ladder resistance conversion time (10bit) reference voltage analog input voltage v v ia v ref v 0 2 10 v cc v ref 40 3.3 conversion time (8bit) 2.8 t conv t samp sampling time 0.3 v ref = v cc sample & hold function not available sample & hold function available (10bit) an 0 to an 7 input anex0, anex1 input, external op-amp connection mode lsb lsb 7 sample & hold function available (8bit) 2 lsb min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 m s ( note ) standard m s m s 3 note: divide the frequency if f(x in ) exceeds 10 mhz, and make ad equal to or lower than 10 mhz. v ref = v cc = 5v v ref = v cc = 5v v ref = v cc = 5v k w k w table 1.28.5. d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v, v ref = 5v at topr = 25 o c, f(x in ) = 20mh z unless otherwise specified) note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the contents of d-a register is except "00 16 " and the vref is unconnected at the a-d control register 1, i vref is sent.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 214 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.28.6. external clock input (note) (note) (note) 26 26 0 0 30 0 25 max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h) t w(l) t f parameter symbol unit standard 5 50 22 22 5 min. data input setup time ns t su(db-bclk) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (rd standard, no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (rd standard, with wait) data input access time (rd standard, when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd C db) = f (bclk) x 2 C 35 10 9 [ns] t ac2(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (note) data input access time (ad standard, cs standard, no wait) ns t ac1(ad-db) (note) ns t ac2(ad-db) data input access time (ad standard, cs standard, with wait) (note) ns t ac3(ad-db) data input access time (ad standard, cs standard, when accessing multiplex bus area) t ac1(ad C db) = f (bclk) C 35 10 9 [ns] t ac2(ad C db) = C 35 10 x n 9 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) t ac3(rd C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t ac3(ad C db) = f (bclk) x 2 C 35 10 x n 9 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) note: calculated according to the bclk frequency as follows: note that inserting wait or using lower operation frequency f(bclk) is needed when calculated value is negative. (note) ns t ac4(cas-db) data input access time (cas standard, dram access) (note) ns t ac4(ras-db) data input access time (ras standard, dram access) (note) ns t ac4(cad-db) data input access time (cad standard, dram access) t ac4(ras C db) = f (bclk) x 2 C 35 10 x m 9 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) t ac4(cas C db) = C 35 10 x n 9 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) t ac4(cad C db) = f (bclk) C 35 10 x l 9 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f (bclk) f (bclk) x 2 ns 0 t h(cas -db) data input hold time table 1.28.7. memory expansion and microprocessor modes v cc = 5v
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 215 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.28.8. timer a input (counter input in event counter mode) table 1.28.9. timer a input (gating input in timer mode) table 1.28.10. timer a input (external trigger input in one-shot timer mode) table 1.28.11. timer a input (external trigger input in pulse width modulation mode) table 1.28.12. timer a input (up/down input in event counter mode) v cc = 5v standard max. ns tai in input low pulse width t w(tal) min. ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns unit standard max. min. ns ns ns unit ns ns tai in input high pulse width t w(tah) parameter symbol tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width symbol parameter t c(ta) tai in input cycle time tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-tin) t h(tin-up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 216 timing requirements (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.28.13. timer b input (counter input in event counter mode) table 1.28.14. timer b input (pulse period measurement mode) table 1.28.15. timer b input (pulse width measurement mode) table 1.28.16. a-d trigger input table 1.28.17. serial i/o _______ table 1.28.18. external interrupt inti inputs v cc = 5v ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t c(ad) t w(adl) symbol parameter unit ad trg input cycle time (trigger able minimum) ad trg input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 1000 125 250 250 200 100 100 0 30 90 80
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 217 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c, cm15 = 1 unless otherwise specified) v cc = 5v figure 1.28.1 table 1.28.19. memory expansion mode and microprocessor mode (no wait) symbol standard measuring condition max. min. pa rameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) -3 ns t h(bclk-cs) chip select output hold time (bclk standard) -3 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time -5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time -3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = f (bclk) 10 9 C 20 [ns] t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) wr signal width ns (note) t w(wr) = f (bclk) x 2 10 9 C 15 [ns]
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 218 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v figure 1.28.1 table 1.28.20. memory expansion mode and microprocessor mode (with wait, accessing external memory) symbol standard measuring condition max. min. pa rameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) C 3 ns t h(bclk-cs) chip select output hold time (bclk standard) C 3 ns t d(bclk-ale) ale signal output delay time 18 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time C 5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time C 3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t d(db C wr) = f (bclk) 10 x n 9 C 20 t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t w(wr) wr signal width (note) ns [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) t w( wr) = 10 x n 9 C 15 f (bclk) x 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 219 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v table 1.28.21. memory expansion mode and microprocessor mode (with wait, accessing external memory, multiplex bus area selected) figure 1.28.1 symbol standard measuring condition max. min. pa rameter unit t d(bclk-ad) address output delay time 18 ns t h(bclk-ad) address output hold time (bclk standard) -3 ns t h(bclk-cs) chip select output hold time (bclk standard) -3 ns t d(bclk-ale) ale signal output delay time (bclk standard) 18 ns t h(bclk-ale) ale signal output hold time (bclk standard) C 2 ns t d(bclk-rd) rd signal output delay time 18 ns t h(bclk-rd) rd signal output hold time -5 ns t d(bclk-wr) wr signal output delay time 18 ns t h(bclk-wr) wr signal output hold time -3 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = 10 x m 9 C 25 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 18 ns t h(rd-ad) address output hold time (rd standard) (note) ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(rd C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 10 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 10 [ns] t d(ad-ale) ale signal output delay time (address standard) ns t h(ale-ad) ale signal output hold time (address standard) ns t dz(rd-ad) address output flowting start time ns (note) (note) 8 t h(wr C cs) = f (bclk) x 2 10 9 C 10 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 10 [ns] t d(ad C ale) = f (bclk) x 2 10 9 C 20 [ns] t h(ale C ad) = f (bclk) x 2 10 9 C 10 [ns] f (bclk) x 2 (note) t h(bclk-db) data output hold time (bclk standard) -5 ns
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 220 switching characteristics (referenced to v cc = 5v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 5v table 1.28.22. memory expansion mode and microprocessor mode (with wait, accessing external memory, dram area selected) symbol standard measuring condition max. min. pa rameter unit t d(bclk-rad) row address output delay time 18 ns t h(bclk-rad) row address output hold time (bclk standard) -3 ns t d(bclk-ras) ras output delay time (bclk standard) -3 ns t su(db-cas) cas after db output setup time 18 ns t h(bclk-db) db signal output hold time (bclk standard) (note) ns 18 t d(bclk-cas) cas output delay time (bclk standard) -3 ns t h(bclk-cas) cas output hold time (bclk standard) (note) ns t d(bclk-dw) data output delay time (bclk standard) ns -7 note: calculated according to the bclk frequency as follows: t su(cas C ras) = f (bclk) x 2 10 9 C 13 [ns] t h(ras-rad) row address output hold time after ras output 18 ns t d(bclk-cad) string address output delay time -3 ns t h(bclk-cad) string address output hold time (bclk standard) (note) ns t h(bclk-ras) ras output hold time (bclk standard) ns t rp ras "h" hold time ns t h(ras C rad) = f (bclk) x 2 10 9 C 13 [ns] t rp = f (bclk) x 2 10 x 3 9 C 20 [ns] t su(cas-ras) cas before ras setup time (refresh) 18 ns (note) t su(db C cas) = f (bclk) 10 9 C 20 [ns] t h(bclk-dw) data output hold time (bclk standard) ns -5 figure 1.28.1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (v cc = 5v) 221 figure 1.28.1. port p0 to p15 measurement circuit p6 p7 p8 p10 p9 p0 p1 p2 p3 p4 p5 30pf p11 p12 p13 p14 p15
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 222 bclk ale -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t su(db-bclk) t d(bclk-rd) 26ns.min *1 csi t d(bclk-cs) 18ns.max *1 adi t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac1(ad-db) *2 t ac1(rd-db) =(tcyc/2-35)ns.max t ac1(ad-db) =(tcyc-35)ns.max wr,wrl, wrh 18ns.max -3ns.min bclk csi t d(bclk-cs) 18ns.max adi t d(bclk-ad) 18ns.max t d(bclk-ale) -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min t h(wr-db) *3 t d(db-wr) =(tcyc-20)ns.min t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2-15)ns.min vcc=5v t h(bclk-rd) t h(rd-db) t h(rd-ad) t h(rd-cs) t h(bclk-wr) t h(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t h(wr-ad) *3 t w(wr) *3 t ac1(rd-db) *2 18ns.max *1 read timing write timing ( written by 2 cycles in selecting no wait) *3:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v memory expansion mode and microprocessor mode (without wait) *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. 18ns.max t d(db-wr) *3 figure 1.28.2. v cc =5v timing diagram (1)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 223 bclk ale 18ns.max -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 26ns.min*1 t ac2(rd-db)*2 csi t d(bclk-cs) 18ns.max*1 adi 18ns.max*1 t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db)*2 t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=5v t h(bclk-rd) t h(rd-db) t su(db-bclk) t h(rd-cs) 0ns.min t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs)*3 t d(db-wr)*3 t h(wr-db)*3 t h(wr-ad)*3 t d(db-wr) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 1 wait) t h(rd-ad) t w(wr)*3 t h(bclk-wr) figure 1.28.3. v cc =5v timing diagram (2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 224 bclk ale 18ns.max -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 26ns.min*1 t ac2(rd-db)*2 csi t d(bclk-cs) 18ns.max*1 adi 18ns.max*1 t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db)*2 t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=5v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs)*3 t d(db-wr)*3 t h(wr-db)*3 t h(wr-ad)*3 t d(db-wr) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 2 wait) t w(wr)*3 figure 1.28.4. v cc =5v timing diagram (3)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 225 figure 1.28.5. v cc =5v timing diagram (4) bclk ale 18ns.max -2ns.min rd 18ns.max -5ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 26ns.min *1 t ac2(rd-db) *2 csi t d(bclk-cs) 18ns.max *1 adi 18ns.max *1 t h(bclk-ad) -3ns.min t h(bclk-cs) -3ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) *2 wr,wrl, wrh 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe dbi t d(bclk-wr) ale 18ns.max -2ns.min vcc=5v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t w(wr) *3 t d(db-wr) *3 t h(wr-db) *3 t h(wr-ad) *3 t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 3 wait) *1:it is a guarantee value with being alone. 35ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t ac2(rd-db) =(tcyc/2 x m-35)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-35)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. t d(db-wr) =(tcyc x n-20)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-10)ns.min t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min t w(wr) =(tcyc/2 x n-15)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) measuring conditions ? v cc =5v10% ? input timing voltage :determined with v ih =2.5v, v il =0.8v ? output timing voltage :determined with v oh =2.0v, v ol =0.8v
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 226 bclk csi 18ns.max adi 18ns.max rd 18ns.max -5ns.min t h(bclk-ad) -3ns.min -3ns.min bhe adi /dbi 0ns.min 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe -5ns.min adi /dbi data output wr,wrl, wrh address address data input 26ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale 18ns.max -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=5v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t h(bclk-db) t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v *1:it depends on operation frequency. read timing write timing memory expansion mode and microprocessor mode (when accessing external memory area with 2 wait, and select multiplexed bus) ) t ac3(ad-db) *1 figure 1.28.6. v cc =5v timing diagram (5)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 227 bclk csi 18ns.max adi 18ns.max rd 18ns.max -5ns.min t h(bclk-ad) -3ns.min -3ns.min bhe adi /dbi 0ns.min 18ns.max -3ns.min bclk csi 18ns.max adi 18ns.max -3ns.min -3ns.min tcyc bhe -5ns.min adi /dbi data output wr,wrl, wrh address address data input 26ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 18ns.max t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(rd-ad) =(tcyc/2-10)ns.min, t h(rd-cs) =(tcyc/2-10)ns.min t ac3(rd-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-35)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale 18ns.max -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-20)ns.min t h(ale-ad) =(tcyc/2-10)ns.min, t h(wr-ad) =(tcyc/2-10)ns.min t h(wr-cs) =(tcyc/2-10)ns.min, t h(wr-db) =(tcyc/2-10)ns.min t d(db-wr) =(tcyc/2 x m-25)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=5v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t h(bclk-db) t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v *1:it depends on operation frequency. read timing write timing memory expansion mode and microprocessor mode (when accessing external memory area with 3 wait, and select multiplexed bus) ) t ac3(ad-db) *1 figure 1.28.7. v cc =5v timing diagram (6)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 228 figure 1.28.8. v cc =5v timing diagram (7) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min vcc=5v ras casl cash hi-z t ac4(cas-db)*2 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) -3ns.min 18ns.max*1 t d(bclk-cad) 18ns.max*1 t d(bclk-ras) 18ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 26ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v read timing memory expansion mode and microprocessor mode (when accessing dram area with 1 wait) *1:it is a guarantee value with being alone. 35ns.max garantees as follows:
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 229 figure 1.28.9. v cc =5v timing diagram (8) bclk dw db mai t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min vcc=5v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t h(bclk-rad) -3ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(ras-rad) *1 t rp *1 18ns.max t d(bclk-dw) t su(db-cas) *1 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) -5ns.min row address string address *1:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v write timing memory expansion mode and microprocessor mode (when accessing dram area with 1 wait)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 230 figure 1.28.10. v cc =5v timing diagram (9) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-35)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-35)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-35)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min vcc=5v ras casl cash hi-z t ac4(cas-db)*2 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) -3ns.min 18ns.max*1 t d(bclk-cad) 18ns.max*1 t d(bclk-ras) 18ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 26ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v read timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait) *1:it is a guarantee value with being alone. 35ns.max garantees as follows:
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 231 figure 1.28.11. v cc =5v timing diagram (10) bclk dw db mai t h(ras-rad) =(tcyc/2-13)ns.min t rp =(tcyc/2 x 3-20)ns.min t su(db-cas) =(tcyc-20)ns.min vcc=5v ras casl cash hi-z t h(bclk-db) -7ns.min 18ns.max t h(bclk-cad) -3ns.min tcyc t d(bclk-rad) t h(bclk-rad) -3ns.min 18ns.max t d(bclk-cad) 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(ras-rad)*1 t rp*1 18ns.max t d(bclk-dw) t su(db-cas)*1 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) -5ns.min row address string address *1:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v write timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 232 figure 1.28.12. v cc =5v timing diagram (11) tcyc 18ns.max t d(bclk-ras) 18ns.max t d(bclk-cas) t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min t su(cas-ras)*1 18ns.max t cyc t d(bclk-cas) t su(cas-ras)*1 t h(bclk-ras) -3ns.min t h(bclk-cas) -3ns.min 18ns.max t d(bclk-ras) bclk dw t su(cas-ras) =(tcyc/2-13)ns.min vcc=5v ras casl cash bclk dw t su(cas-ras) =(tcyc/2-13)ns.min ras casl cash *1:it depends on operation frequency. measuring conditions ?v cc =5v10% ?input timing voltage :determined with v ih =2.5v, v il =0.8v ?output timing voltage :determined with v oh =2.0v, v ol =0.8v refresh timing (cas before ras refresh) memory expansion mode and microprocessor mode *1:it depends on operation frequency. refresh timing (self-refresh)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 233 figure 1.28.13. v cc =5v timing diagram (12) v cc = 5v t su(d?) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 5v) 234 figure 1.28.14. v cc =5v timing diagram (13) v cc = 5v t h(bclk?old) t su(hold?clk) t d(bclk?lda) t d(bclk?lda) hi? measuring conditions : ?v cc = 5v10% ?input timing voltage : determined with v il =1.0v, v ih =4.0v ?output timing voltage : determined with v ol =2.5v, v oh =2.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with or without wait) (valid only with wait) rdy input t su(rdy?clk) t h(bclk?dy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 3v) 235 v cc = 3v table 1.28.23. electrical characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c, f(x in ) = 10mh z unless otherwise specified) v v x out 2.5 2.5 v 0.5 v x out 0.5 0.5 2.5 i oh = - 1ma i oh = - 0.1ma i oh = - 50 m a i ol =1ma highpower lowpower highpower lowpower highpower lowpower x cout 3.0 1.6 v ta0 out -ta4 out ,nmi, 0.2 1.0 v 0.2 1.8 v 4.0 2.0 v reset p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , x in , reset, cnvss, byte int 0 -int 5 ,ad trg , cts 0 -cts 4 , clk 0 -clk 4 , hold, rdy, ta0 in -ta4 in , tb0 in -tb5 in , v i =3v v i =0v - 4.0 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , x in , reset, cnvss, byte 10.0 3.0 m w m w 120.0 k w p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 ,p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 ,p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 , v x cout 0 0 highpower lowpower v i =0v 66.0 500.0 ki 0 -ki 3, rxd0-rxd4 v oh v oh v ol v ol v t+- v t- symbol high output voltage high output voltage high output voltage low output voltage low output voltage low output voltage hysteresis i ih i il v ram icc v t+- v t- r fxin r fxcin r pullup hysteresis high input current low input current pull-up resistance x in x cin feedback resistance feedback resistance ram retention voltage power supply current when clock is stopped m a m a with no load applied with no load applied with no load applied with no load applied parameter unit standard min. typ. max. measuring condition p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 0 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 p0 0 -p0 7 , p1 0 -p1 7 , p2 0 -p2 7 , p3 0 -p3 7 , p4 0 -p4 7 , p5 0 -p5 7 , p6 0 -p6 7 , p7 2 -p7 7 , p8 0 -p8 4 , p8 6 , p8 7 , p9 0 -p9 7 , p10 0 -p10 7 , p11 0 -p11 4 , p12 0 -p12 7 , p13 0 -p13 7 , p14 0 -p14 6 , p15 0 -p15 7 scl 2 -scl 4 , sda 2 -sda 3 m a ma 20.0 12.0 20.0 1.5 f(x in )=10mhz f(x cin )=32khz in single-chip mode, the output pins are open and other pins are v ss square wave, no division square wave f(x cin )=32khz topr=85 c, when clock is stopped when a wait instruction is executed. oscillation drive capacity is low. m a m a 3.0 f(x cin )=32khz when a wait instruction is executed. oscillation drive capacity is high. m a mask rom 128 kb version mask rom 256 kb version flash memory version ma 14.0 23.0 ma 14.0 23.0 45.0 mask rom 128 kb version mask rom 256 kb version flash memory version 60.0 ma 3.5 m a i ol = 0.1ma i ol = 50 m a 1.0 2.0 1.0 topr=25 c, when clock is stopped mask rom 128 kb version romless ram 10kb version mask rom 256 kb version romless ram 24kb version flash memory version measuring condition: electrical characteristics (vcc = 3v)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer electrical characteristics (vcc = 3v) 236 table 1.28.24. a-d conversion characteristics (referenced to v cc = av cc = v ref = 3v, v ss = av ss = 0v at topr = 25 o c, f(x in ) = 10mh z unless otherwise specified) v cc = 3v standard min. typ. max t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.0 8 3 symbol parameter measuring condition unit 20 10 4 (note) r ladder ladder resistance reference voltage analog input voltage v v ia v ref v 0 2.7 10 v cc v ref 40 conversion time (8bit) 9.8 t conv v ref = v cc standard min. typ. max resolution absolute accuracy bits lsb v ref = v cc 2 10 symbol parameter measuring condition unit v ref = v cc = 3v, f ad = f ad /2 sample & hold function not available (8 bit) m s m s k w k w table 1.28.25. d-a conversion characteristics (referenced to v cc = 3v, v ss = av ss = 0v, v ref = 3v at topr = 25 o c, f(x in ) = 10mh z unless otherwise specified) note : this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the contents of d-a register 1 is except "00 16 " and the vref is unconnected at the a-d control register 1, iv ref is sent.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 237 timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) (note) (note) (note) 40 60 0 0 80 0 100 max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h) t w(l) t f parameter symbol unit standard 18 100 40 40 18 min. data input setup time ns t su(db-bclk) t su(rdy-bclk ) parameter symbol unit max. standard ns rdy input setup time data input hold time ns t h(rd-db) t h(bclk -rdy) ns rdy input hold time ns hold input setup time t su(hold-bclk ) ns hold input hold time t h(bclk-hold ) data input access time (rd standard, no wait) ns t ac1(rd-db) ns ns t ac2(rd-db) t ac3(rd-db) data input access time (rd standard, with wait) data input access time (rd standard, when accessing multiplex bus area) ns t d(bclk-hlda ) hlda output delay time t ac1(rd ?db) = f (bclk) x 2 ?55 10 9 [ns] t ac2(rd ?db) = f (bclk) x 2 ?55 10 x m 9 [ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively) (note) data input access time (ad standard, cs standard, no wait) ns t ac1(ad-db) (note) ns t ac2(ad-db) data input access time (ad standard, cs standard, with wait) (note) ns t ac3(ad-db) data input access time (ad standard, cs standard, when accessing multiplex bus area) t ac1(ad ?db) = f (bclk) ?55 10 9 [ns] t ac2(ad ?db) = ?55 10 x n 9 [ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively) t ac3(rd ?db) = f (bclk) x 2 ?55 10 x m 9 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t ac3(ad ?db) = f (bclk) x 2 ?55 10 x n 9 [ns] (n=5 and 7 when 2 wait and 3 wait, respectively) note: calculated according to the bclk frequency as follows: note that inserting wait or using lower operation frequency f(bclk) is needed when calculated value is negative. (note) ns t ac4(cas-db) data input access time (cas standard, dram access) (note) ns t ac4(ras-db) data input access time (ras standard, dram access) (note) ns t ac4(cad-db) data input access time (cad standard, dram access) t ac4(ras ?db) = f (bclk) x 2 ?55 10 x m 9 [ns] (m=3 and 5 when 1 wait and 2 wait, respectively) t ac4(cas ?db) = ?55 10 x n 9 [ns] (n=1 and 3 when 1 wait and 2 wait, respectively) t ac4(cad ?db) = f (bclk) ?55 10 x l 9 [ns] (l=1 and 2 when 1 wait and 2 wait, respectively) f (bclk) f (bclk) x 2 0 data input hold time ns t h(cas-db) v cc = 3v table 1.28.26. external clock input table 1.28.27. memory expansion and microprocessor modes
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 238 v cc = 3v timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) standard max. min. unit parameter symbol ns t w(tal) tai in input low pulse width 60 ns t c(ta) tai in input cycle time 150 ns t w(tah) tai in input high pulse width 60 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 600 ns t w(tah) tai in input high pulse width 300 ns t w(tal) tai in input low pulse width 300 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 300 ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t c(up) tai out input cycle time 3000 ns t w(uph) tai out input high pulse width 1500 ns t w(upl) tai out input low pulse width 1500 ns t su(up-t in ) tai out input setup time 600 ns t h(t in- up) tai out input hold time 600 table 1.28.29. timer a input (gating input in timer mode) table 1.28.30. timer a input (external trigger input in one-shot timer mode) table 1.28.31. timer a input (external trigger input in pulse width modulation mode) table 1.28.32. timer a input (up/down input in event counter mode) table 1.28.28. timer a input (counter input in event counter mode)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 239 timing requirements (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) v cc = 3v standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time (counted on one edge) 150 ns t w(tbh) tbi in input high pulse width (counted on one edge) 60 ns t w(tbl) tbi in input low pulse width (counted on one edge) 60 t w(tbh) ns tbi in input high pulse width (counted on both edges) 160 t w(tbl) ns tbi in input low pulse width (counted on both edges) 160 t c(tb) ns tbi in input cycle time (counted on both edges) 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t c(ad) ad trg input cycle time (trigger able minimum) 1500 ns t w(adl) ad trg input low pulse width 200 standard max. min. parameter symbol unit ns t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 standard max. min. parameter symbol unit ns t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 t h(c-q) ns txdi hold time 0 t su(d-c) ns rxdi input setup time 50 t h(c-d) ns rxdi input hold time 90 t d(c-q) ns txdi output delay time 160 table 1.28.33. timer b input (counter input in event counter mode) table 1.28.34. timer b input (pulse period measurement mode) table 1.28.35. timer b input (pulse width measurement mode) table 1.28.36. a-d trigger input table 1.28.37. serial i/o _______ table 1.28.38. external interrupt inti inputs
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 240 symbol standard measuring condition max. min. pa rameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time C 3 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = f (bclk) 10 9 C 40 [ns] t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(wr C db) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 20 [ns] t w(wr) wr signal width t w(wr) = f (bclk) x 2 10 9 C 20 [ns] t h(wr-db) data output hold time (wr standard) ns (note) switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c, cm15 = 1 unless otherwise specified) v cc = 3v figure 1.28.1 table 1.28.39. memory expansion and microprocessor modes (with no wait)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 241 switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c, unless otherwise specified) v cc = 3v figure 1.28.1 table 1.28.40. memory expansion and microprocessor modes (with wait, accessing external memory) symbol standard measuring condition max. min. pa rameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time 25 ns t h(bclk-ale) ale signal output hold time C 2 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time C 3 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: [ns] (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (rd standard) 0 ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) 0 ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t d(db C wr) = f (bclk) 10 x n 9 C 40 t h(wr C db) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C cs) = f (bclk) x 2 10 9 C 20 [ns] t w(wr) wr signal width [ns] (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively) t w( wr) = 10 x n 9 C 20 (note) ns f (bclk) x 2
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 242 v cc = 3v switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c, unless otherwise specified) table 1.28.41. memory expansion and microprocessor modes (with wait, accessing external memory, multiplex bus area selected) symbol standard measuring condition max. min. parameter unit t d(bclk-ad) address output delay time 25 ns t h(bclk-ad) address output hold time (bclk standard) 0 ns t h(bclk-cs) chip select output hold time (bclk standard) 0 ns t d(bclk-ale) ale signal output delay time (bclk standard) 25 ns t h(bclk-ale) ale signal output hold time (bclk standard) C 2 ns t d(bclk-rd) rd signal output delay time 25 ns t h(bclk-rd) rd signal output hold time 0 ns t d(bclk-wr) wr signal output delay time 25 ns t h(bclk-wr) wr signal output hold time 0 ns t h(wr-db) data output hold time (wr standard) (note) ns t d(db-wr) data output delay time (wr standard) ns (note) note: calculated according to the bclk frequency as follows: t d(db C wr) = 10 x m 9 C 40 [ns] (m=3 and 5 when 2 wait and 3 wait, respectively) t d(bclk-cs) chip select output delay time 25 ns t h(rd-ad) address output hold time (rd standard) (note) ns t h(wr-ad) address output hold time (wr standard) (note) ns t h(rd-cs) chip select output hold time (rd standard) ns t h(wr-cs) chip select output hold time (wr standard) (note) ns t h(rd C ad) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C ad) = f (bclk) x 2 10 9 C 20 [ns] t h(rd C cs) = f (bclk) x 2 10 9 C 20 [ns] t d(ad-ale) ale signal output delay time (address standard) ns t h(ale-ad) ale signal output hold time (address standard) ns t dz(rd-ad) address output flowting start time ns (note) (note) 8 t h(wr C cs) = f (bclk) x 2 10 9 C 20 [ns] t h(wr C db) = f (bclk) x 2 10 9 C 20 [ns] t d(ad C ale) = f (bclk) x 2 10 9 C 27 [ns] t h(ale C ad) = f (bclk) x 2 10 9 C 20 [ns] f (bclk) x 2 (note) t h(bclk-db) db signal output hold time (bclk standard) ns 0 figure 1.28.1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 243 v cc = 3v switching characteristics (referenced to v cc = 3v, v ss = 0v at topr = 25 o c unless otherwise specified) table 1.28.42. memory expansion and microprocessor modes (with wait, accessing external memory, dram area selected) symbol standard measuring condition max. min. pa rameter unit t d(bclk-rad) row address output delay time 25 ns t h(bclk-rad) row address output hold time (bclk standard) 0 ns t d(bclk-ras) ras output delay time (bclk standard) 0 ns t su(db-cas) cas after db output setup time 25 ns t h(bclk-db) db signal output hold time (bclk standard) (note) ns 25 t d(bclk-cas) cas output delay time (bclk standard) C 3 ns t h(bclk-cas) cas output hold time (bclk standard) (note) ns t d(bclk-dw) data output delay time (bclk standard) ns C 7 note: calculated according to the bclk frequency as follows: t su(cas C ras) = f (bclk) x 2 10 9 C 25 [ns] t h(ras-rad) row address output hold time after ras output 25 ns t d(bclk-cad) string address output delay time 0 ns t h(bclk-cad) string address output hold time (bclk standard) (note) ns t h(bclk-ras) ras output hold time (bclk standard) ns t rp ras "h" hold time ns t h(ras C rad) = f (bclk) x 2 10 9 C 25 [ns] t rp = f (bclk) x 2 10 x 3 9 C 40 [ns] t su(cas-ras) cas before ras setup time (refresh) 25 ns (note) t su(db C cas) = f (bclk) 10 9 C 40 [ns] t h(bclk-dw) data output hold time (bclk standard) ns 0 figure 1.28.1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 244 figure 1.28.15. v cc =3v timing diagram (1) bclk ale -2ns.min rd 25ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t su(db-bclk) t d(bclk-rd) 40ns.min *1 csi t d(bclk-cs) 25ns.max *1 adi t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) 0ns.min t ac1(ad-db) *2 t ac1(rd-db) =(tcyc/2-55)ns.max t ac1(ad-db) =(tcyc-55)ns.max wr,wrl, wrh 25ns.max 0ns.min bclk csi t d(bclk-cs) 25ns.max adi t d(bclk-ad) 25ns.max t d(bclk-ale) 0ns.min 0ns.min tcyc bhe t d(db-wr) *3 dbi t d(bclk-wr) ale -2ns.min t h(wr-db) *3 t d(db-wr) =(tcyc-40)ns.min t h(wr-db) =(tcyc/2-20)ns.min t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min t w(wr) =(tcyc/2-20)ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t h(rd-cs) t h(bclk-wr) t h(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t h(wr-ad) *3 t ac1(rd-db) *2 25ns.max *1 read timing write timing ( written by 2 cycles in selecting no wait) *3:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode (without wait) *1:it is a guarantee value with being alone. 55ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. 25ns.max t w(wr)*3 25ns.max
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 245 figure 1.28.16. v cc =3v timing diagram (2) bclk ale 25ns.max -2ns.min rd 25ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 40ns.min *1 t ac2(rd-db) *2 csi t d(bclk-cs) 25ns.max *1 adi 25ns.max *1 t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) *2 t ac2(rd-db) =(tcyc/2 x m-55)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 25ns.max 0ns.min bclk csi 25ns.max adi 25ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) ale 25ns.max -2ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t d(db-wr) *3 t h(wr-db) *3 t h(wr-ad) *3 t d(db-wr) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-20)ns.min t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min t w(wr) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it is a guarantee value with being alone. 55ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 1 wait) t w(wr) *3
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 246 figure 1.28.17. v cc =3v timing diagram (3) bclk ale 25ns.max -2ns.min rd 25ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 40ns.min *1 t ac2(rd-db) *2 csi t d(bclk-cs) 25ns.max *1 adi 25ns.max *1 t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) *2 t ac2(rd-db) =(tcyc/2 x m-55)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) wr,wrl, wrh 25ns.max 0ns.min bclk csi 25ns.max adi 25ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) ale 25ns.max -2ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t d(db-wr) *3 t h(wr-db) *3 t h(wr-ad) *3 t d(db-wr) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-20)ns.min t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min t w(wr) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it is a guarantee value with being alone. 55ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 2 wait) t w(wr) *3
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 247 figure 1.28.18. v cc =3v timing diagram (4) bclk ale 25ns.max -2ns.min rd 25ns.max -3ns.min hi-z db 0ns.min 0ns.min t d(bclk-ale) t h(bclk-ale) t d(bclk-rd) 40ns.min *1 t ac2(rd-db) *2 csi t d(bclk-cs) 25ns.max *1 adi 25ns.max *1 t h(bclk-ad) 0ns.min t h(bclk-cs) 0ns.min bhe tcyc t d(bclk-ad) t ac2(ad-db) *2 wr,wrl, wrh 25ns.max 0ns.min bclk csi 25ns.max adi 25ns.max 0ns.min 0ns.min tcyc bhe dbi t d(bclk-wr) ale 25ns.max -2ns.min vcc=3v t h(bclk-rd) t h(rd-db) t h(rd-ad) t su(db-bclk) t h(rd-cs) 0ns.min t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t d(bclk-ale) t h(bclk-ad) t h(bclk-cs) t h(wr-cs) *3 t d(db-wr) *3 t h(wr-db) *3 t h(wr-ad) *3 t h(bclk-ale) read timing write timing memory expansion mode and microprocessor mode (with 3 wait) t w(wr) *3 *1:it is a guarantee value with being alone. 55ns.max garantees as t d(bclk-ad) +t su(db-bclk) . *2:it depends on operation frequency. t ac2(rd-db) =(tcyc/2 x m-55)ns.max (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively.) t ac2(ad-db) =(tcyc x n-55)ns.max (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively.) *3:it depends on operation frequency. t d(db-wr) =(tcyc x n-40)ns.min (n=1, 2 and 3 when 1 wait, 2 wait and 3 wait, respectively.) t h(wr-db) =(tcyc/2-20)ns.min t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min t w(wr) =(tcyc/2 x n-20)ns.min (n=1, 3 and 5 when 1 wait, 2 wait and 3 wait, respectively.) measuring conditions ? v cc =3v10% ? input timing voltage :determined with v ih =1.5v, v il =0.5v ? output timing voltage :determined with v oh =1.5v, v ol =1.5v
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 248 figure 1.28.19. v cc =3v timing diagram (5) bclk csi 25ns.max adi 25ns.max rd 25ns.max -3ns.min t h(bclk-ad) 0ns.min 0ns.min bhe adi /dbi 0ns.min 25ns.max 0ns.min bclk csi 25ns.max adi 25ns.max 0ns.min 0ns.min tcyc bhe 0ns.min adi /dbi data output wr,wrl, wrh address address data input 40ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 25ns.max t d(ad-ale) =(tcyc/2-27)ns.min t h(ale-ad) =(tcyc/2-20)ns.min, t h(rd-ad) =(tcyc/2-20)ns.min, t h(rd-cs) =(tcyc/2-20)ns.min t ac3(rd-db) =(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-27)ns.min t h(ale-ad) =(tcyc/2-20)ns.min, t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min, t h(wr-db) =(tcyc/2-20)ns.min t d(db-wr) =(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=3v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t h(bclk-db) t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it depends on operation frequency. read timing write timing memory expansion mode and microprocessor mode (when accessing external memory area with 2 wait, and select multiplexed bus) 25ns.max t ac3(ad-db) *1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 249 figure 1.28.20. v cc =3v timing diagram (6) bclk csi 25ns.max adi 25ns.max rd 25ns.max -3ns.min t h(bclk-ad) 0ns.min 0ns.min bhe adi /dbi 0ns.min 25ns.max 0ns.min bclk csi 25ns.max adi 25ns.max 0ns.min 0ns.min tcyc bhe 0ns.min adi /dbi data output wr,wrl, wrh address address data input 40ns.min t d(bclk-rd) t h(wr-cs) *2 address t d(ad-ale) *2 address t su(db-bclk) t ac3(rd-db) *1 t dz(rd-ad) 8ns.max ale -2ns.min t d(bclk-ale) 25ns.max t d(ad-ale) =(tcyc/2-27)ns.min t h(ale-ad) =(tcyc/2-20)ns.min, t h(rd-ad) =(tcyc/2-20)ns.min, t h(rd-cs) =(tcyc/2-20)ns.min t ac3(rd-db) =(tcyc/2 x m-55)ns.max (m=3 and 5 when 2 wait and 3 wait, respectively.) t ac3(ad-db) =(tcyc/2 x n-55)ns.max (n=5 and 7 when 2 wait and 3 wait, respectively.) ale -2ns.min t d(bclk-ale) t h(ale-ad) *2 t d(ad-ale) =(tcyc/2-27)ns.min t h(ale-ad) =(tcyc/2-20)ns.min, t h(wr-ad) =(tcyc/2-20)ns.min t h(wr-cs) =(tcyc/2-20)ns.min, t h(wr-db) =(tcyc/2-20)ns.min t d(db-wr) =(tcyc/2 x m-40)ns.min (m=3 and 5 when 2 wait and 3 wait, respectively.) vcc=3v t d(bclk-cs) t d(ad-ale) *1 t h(ale-ad) *1 t h(bclk-rd) t h(rd-ad) *1 t h(rd-db) t d(bclk-ad) t h(bclk-cs) t h(rd-cs) *1 t d(bclk-wr) t h(bclk-wr) t d(bclk-cs) t d(bclk-ad) t h(bclk-ad) t h(bclk-cs) t h(wr-ad) *2 t h(bclk-db) t d(db-wr) *2 t h(wr-db) *2 t h(bclk-ale) t h(bclk-ale) tcyc *2:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v *1:it depends on operation frequency. read timing write timing memory expansion mode and microprocessor mode (when accessing external memory area with 3 wait, and select multiplexed bus) 25ns.max t ac3(ad-db) *1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 250 figure 1.28.21. v cc =3v timing diagram (7) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-25)ns.min t rp =(tcyc/2 x 3-40)ns.min vcc=3v ras casl cash hi-z t ac4(cas-db)*2 25ns.max*1 t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) 0ns.min 25ns.max*1 t d(bclk-cad) 25ns.max*1 t d(bclk-ras) 25ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 40ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v read timing memory expansion mode and microprocessor mode (when accessing dram area with 1 wait) *1:it is a guarantee value with being alone. 55ns.max garantees as follows:
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 251 figure 1.28.22. v cc =3v timing diagram (8) bclk dw db mai t h(ras-rad) =(tcyc/2-25)ns.min t rp =(tcyc/2 x 3-40)ns.min t su(db-cas) =(tcyc-40)ns.min vcc=3v ras casl cash hi-z t h(bclk-db) -7ns.min 25ns.max t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t h(bclk-rad) 0ns.min 25ns.max t d(bclk-cad) 25ns.max t d(bclk-ras) 25ns.max t d(bclk-cas) t rp*1 25ns.max t d(bclk-dw) t su(db-cas)*1 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) 0ns.min row address string address *1:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v write timing memory expansion mode and microprocessor mode (when accessing dram area with 1 wait) t h(ras-rad)*1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 252 figure 1.28.23. v cc =3v timing diagram (9) bclk dw db mai t d(bclk-ras) + t su(db-bclk) t d(bclk-cas) + t su(db-bclk) t d(bclk-cad) + t su(db-bclk) t ac4(ras-db) =(tcyc/2 x m-55)ns.max (m=3 and 5 when 1 wait and 2 wait, respectively.) t ac4(cas-db) =(tcyc/2 x n-55)ns.max (n=1 and 3 when 1 wait and 2 wait, respectively.) t ac4(cad-db) =(tcyc x l-55)ns.max (l=1 and 2 when 1 wait and 2 wait, respectively.) t h(ras-rad) =(tcyc/2-25)ns.min t rp =(tcyc/2 x 3-40)ns.min vcc=3v ras casl cash hi-z t ac4(cas-db)*2 25ns.max*1 t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t ac4(ras-db)*2 row address string address t h(bclk-rad) 0ns.min 25ns.max*1 t d(bclk-cad) 25ns.max*1 t d(bclk-ras) 25ns.max*1 t d(bclk-cas) t h(ras-rad)*2 t rp*2 t ac4(cad-db)*2 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min 0ns.min t su(db-bclk) 40ns.min*1 t h(cas-db) *2:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v read timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait) *1:it is a guarantee value with being alone. 55ns.max garantees as follows:
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 253 figure 1.28.24. v cc =3v timing diagram (10) bclk dw db mai t h(ras-rad) =(tcyc/2-25)ns.min t rp =(tcyc/2 x 3-40)ns.min t su(db-cas) =(tcyc-40)ns.min vcc=3v ras casl cash hi-z t h(bclk-db) -7ns.min 25ns.max t h(bclk-cad) 0ns.min tcyc t d(bclk-rad) t h(bclk-rad) 0ns.min 25ns.max t d(bclk-cad) 25ns.max t d(bclk-ras) 25ns.max t d(bclk-cas) t rp*1 25ns.max t d(bclk-dw) t su(db-cas)*1 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min t h(bclk-dw) 0ns.min row address string address *1:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v write timing memory expansion mode and microprocessor mode (when accessing dram area with 2 wait) t h(ras-rad)*1
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 254 figure 1.28.25. v cc =3v timing diagram (11) tcyc 25ns.max t d(bclk-ras) 25ns.max t d(bclk-cas) t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min t su(cas-ras)*1 25ns.max t cyc t d(bclk-cas) t su(cas-ras)*1 t h(bclk-ras) 0ns.min t h(bclk-cas) -3ns.min 25ns.max t d(bclk-ras) bclk dw t su(cas-ras) =(tcyc/2-25)ns.min vcc=3v ras casl cash bclk dw t su(cas-ras) =(tcyc/2-25)ns.min ras casl cash *1:it depends on operation frequency. measuring conditions ?v cc =3v10% ?input timing voltage :determined with v ih =1.5v, v il =0.5v ?output timing voltage :determined with v oh =1.5v, v ol =1.5v refresh timing (cas before ras refresh) memory expansion mode and microprocessor mode *1:it depends on operation frequency. refresh timing (self-refresh)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 255 figure 1.28.26. v cc =3v timing diagram (12) t su(d?) tai in input tai out input during event counter mode tbi in input clki txdi rxdi t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ad) t w(adl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) t d(c?) t h(c?) t h(c?) t h(t in ?p) t su(up? in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) inti input ad trg input v cc = 3v
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer timing (vcc = 3v) 256 figure 1.28.27. v cc =3v timing diagram (13) v cc = 3v measuring conditions : ?v cc =3v10% ?input timing voltage : determined with v ih =2.4v, v il =0.6v ?output timing voltage : determined with v oh =1.5v, v ol =1.5v memory expansion mode and microprocessor mode bclk hold input hlda output p0, p1, p2, p3, p4, p5 0 to p5 2 (valid with or without wait) (valid only with wait) rdy input t su(rdy?clk) t h(bclk?dy) bclk rd (multiplexed bus) (multiplexed bus) wr, wrl, wrh wr, wrl, wrh (separate bus) rd (separate bus) hi? t h(bclk?old) t su(hold?clk) t d(bclk?lda) t d(bclk?lda)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description (flash memory version) 257 item power supply voltage program/erase voltage flash memory operation mode erase block division program method erase method program/erase control method protect method number of commands program/erase count rom code protect performance 5v version: f(x in )=20mhz, without wait, 4.2v to 5.5v f(x in )=10mhz, without wait, 2.7v to 5.5v 5v version: 4.2v to 5.5 v f( bclk )=12.5mhz, with one wait f( bclk )=6.25mhz, without wait three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.29.3 one division (8 kbytes) (note 1) in units of pages (in units of 256 bytes) collective erase/block erase program/erase control by software command protected for each block by lock bit 8 commands 100 times parallel i/o and standard serial modes are supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area data holding 10 years table 1.29.1. outline performance of the m16c/80 (flash memory version) outline performance table 1.29.1 shows the outline performance of the m16c/80 (flash memory version).
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description (flash memory version) 258 the following shows mitsubishi plans to develop a line of m16c/80 products (flash memory version). (1) rom capacity (2) package 144p6q ... plastic molded qfp figure 1.29.1. rom expansion the following lists the m16c/80 products to be supported in the future. rom size (bytes) m30805fggp flash memory version external rom 256k 128k 96k 64k 32k m30802fcgp table 1.29.2. product list ** : under development m30802fcgp m30805fggp 10 kbytes 128 kbytes 144p6q-a 24 kbytes 256 kbytes 144p6q-a ** ** ram capacity rom capacity package type remarks type no as of june, 2000 figure 1.29.2. type no., memory size, and package package type: fp : package 100p6s-a gp : package 100p6q-a, 144p6q-a rom no. omitted for blank external rom version and flash memory version rom capacity: c : 128k bytes g : 256k bytes memory type: m : mask rom version s : external rom version f : flash memory version type no. m 3 0 8 0 2 m c ? x x x f p m16c/80 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer description (flash memory version) 259 flash memory the m16c/80 (flash memory version) contains the flash memory that can be rewritten with a single voltage of 5 v. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and a cpu rewrite mode in which the flash memory can be manipulated by the central pro- cessing unit (cpu). each modes are detailed in the pages to follow. the flash memory is divided into several blocks as shown in figure 1.29.3, so that memory can be erased one block at a time. each block has a lock bit to enable or disable execution of an erase or program operation, allowing for data in each block to be protected. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application system. this boot rom area can be rewritten in only parallel i/o mode. figure 1.29.3. block diagram of flash memory version 0fc0000 16 0fd0000 16 block 6 : 64k byte block 5 : 64k byte 0fe0000 16 block 4 : 64k byte 0ff0000 16 block 3 : 32k byte 0ff8000 16 block 2 : 8k byte 0ffa000 16 block 1 : 8k byte block 0 : 16k byte 0ffc000 16 user rom area 8k byte 0ffe000 16 0ffffff 16 0ffffff 16 boot rom area flash memory start address 0fe0000 16 0fc0000 16 note 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. flash memory size 256kbytes 128kbytes
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 260 cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, only the user rom area shown in figure 1.29.3 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block erase commands are issued for only the user rom area and each block area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to any area other than the internal flash memory before it can be executed. microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure 1.29.3 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low. in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p5 5 pin low, the cnv ss pin high, and the p5 0 pin high, the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. the control program in the boot rom area can also be used to rewrite the user rom area. block address block addresses refer to the maximum even address of each block. these addresses are used in the block erase command, lock bit program command, and read lock status command.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 261 outline performance (cpu rewrite mode) in the cpu rewrite mode, the cpu erases, programs and reads the internal flash memory as instructed by software commands. operations must be executed from a memory other than the internal flash memory, such as the internal ram. when the cpu rewrite mode select bit (bit 1 at address 0377 16 ) is set to 1, transition to cpu rewrite mode occurs and software commands can be accepted. in the cpu rewrite mode, write to and read from software commands and data into even-numbered ad- dress (0 for byte address a0) in 16-bit units. always write 8-bit software commands into even-numbered address. commands are ignored with odd-numbered addresses. use software commands to control program and erase operations. whether a program or erase operation has terminated normally or in error can be verified by reading the status register. figure 1.30.1 shows the flash memory control register 0 and the flash memory control register 1. _____ bit 0 of the flash memory control register 0 is the ry/by status flag used exclusively to read the operating status of the flash memory. during programming and erase operations, it is 0. otherwise, it is 1. bit 1 of the flash memory control register 0 is the cpu rewrite mode select bit. the cpu rewrite mode is entered by setting this bit to 1, so that software commands become acceptable. in cpu rewrite mode, the cpu becomes unable to access the internal flash memory directly. therefore, write bit 1 in an area other than the internal flash memory. to set this bit to 1, it is necessary to write 0 and then write 1 in succession. the bit can be set to 0 by only writing a 0 . bit 2 of the flash memory control register 0 is a lock bit disable bit. by setting this bit to 1, it is possible to disable erase and write protect (block lock) effectuated by the lock bit data. the lock bit disable select bit only disables the lock bit function; it does not change the lock data bit value. however, if an erase operation is performed when this bit =1, the lock bit data that is 0 (locked) is set to 1 (unlocked) after erasure. to set this bit to 1, it is necessary to write 0 and then write 1 in succession. this bit can be manipulated only when the cpu rewrite mode select bit = 1. bit 3 of the flash memory control register 0 is the flash memory reset bit used to reset the control circuit of the internal flash memory. this bit is used when exiting cpu rewrite mode and when flash memory access has failed. when the cpu rewrite mode select bit is 1, writing 1 for this bit resets the control circuit. to release the reset, it is necessary to set this bit to 0. bit 5 of the flash memory control register 0 is a user rom area select bit which is effective in only boot mode. if this bit is set to 1 in boot mode, the area to be accessed is switched from the boot rom area to the user rom area. when the cpu rewrite mode needs to be used in boot mode, set this bit to 1. note that if the microcomputer is booted from the user rom area, it is always the user rom area that can be accessed and this bit has no effect. when in boot mode, the function of this bit is effective regardless of whether the cpu rewrite mode is on or off. use the control program except in the internal flash memory to rewrite this bit. bit 3 of the flash memory control register 1 turns power supply to the internal flash memory on/off. when this bit is set to 1, power is not supplied to the internal flash memory, thus power consumption can be reduced. however, in this state, the internal flash memory cannot be accessed. to set this bit to 1, it is necessary to write 0 and then write 1 in succession. use this bit mainly in the low speed mode (when x cin is the block count source of bclk). when the cpu is shifted to the stop or wait modes, power to the internal flash memory is automatically shut off. it is reconnected automatically when cpu operation is restored. therefore, it is not particularly neces- sary to set flash memory control register 1.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 262 flash memory control register 0 symbol address when reset fmr0 0377 16 xx000001 2 w r b7 b6 b5 b4 b3 b2 b1 b0 fmr00 bit symbol bit name function rw 0: busy (being written or erased) 1: ready cpu rewrite mode select bit (note 1) 0: normal mode (software commands invalid) 1: cpu rewrite mode (software commands acceptable) fmr01 0: boot rom area is accessed 1: user rom area is accessed lock bit disable bit (note 2) 0: block lock by lock bit data is enabled 1: block lock by lock bit data is disabled flash memory reset bit (note 3) 0: normal operation 1: reset nothing is assigned. when write, set "0". when read, values are indeterminate. user rom area select bit ( note 4) (effective in only boot mode) fmr02 fmr03 fmr05 0 note 1: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession. when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. use the control program except in the internal flash memory for write to this bit. note 2: for this bit to be set to ?? the user needs to write a ??and then a ??to it in succession when the cpu rewrite mode select bit = ?? when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 3: effective only when the cpu rewrite mode select bit = 1. set this bit to 0 subsequently after setting it to 1 (reset). note 4: use the control program except in the internal flash memory for write to this bit. a a a a a a a a a a a a a ry/by status flag flash memory control register 1 symbol address when reset fmr1 0376 16 xxxx0xxx 2 w r b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function rw flash memory power supply-off bit (note) 0: flash memory power supply is connected 1: flash memory power supply-off fmr13 0 note : for this bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession. when it is not this procedure, it is not enacted in 1. this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. use the control program except in the internal flash memory for write to this bit. during parallel i/o mode,programming,erase or read of flash memory is not controlled by this bit,only by external pins. a a a a 0 0 00 0 reserved bit must always be set to 0 a reserved bit must always be set to 0 reserved bit must always be set to 0 0 figure 1.30.1. flash memory control registers figure 1.30.2 shows a flowchart for setting/releasing the cpu rewrite mode. figure 1.30.3 shows a flow- chart for shifting to the low speed mode. always perform operation as indicated in these flowcharts.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 263 end start execute read array command or reset flash memory by setting flash memory reset bit (by writing ??and then ??in succession) (note 3) single-chip mode, memory expansion mode, or boot mode set processor mode register (note 1) using software command execute erase, program, or other operation (set lock bit disable bit as required) jump to transferred control program in ram (subsequent operations are executed by control program in this ram) transfer cpu rewrite mode control program to internal ram note 1: during cpu rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000c 16 ): 6.25 mhz or less when wait bit (bit 2 at address 0005 16 ) = ??(without internal access wait state) 12.5 mhz or less when wait bit (bit 2 at address 0005 16 ) = ??(with internal access wait state) note 2: for cpu rewrite mode select bit to be set to ?? the user needs to write a ??and then a ??to it in succession. when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 3: before exiting the cpu rewrite mode after completing erase or program operation, always be sure to execute a read array command or reset the flash memory. note 4: ??can be set. however, when this bit is ?? user rom area is accessed. (boot mode only) write ??to user rom area select bit (note 4) write ??to cpu rewrite mode select bit (boot mode only) set user rom area select bit to ? set cpu rewrite mode select bit to ??(by writing ??and then ??in succession)(note 2) *1 *1 program in rom program in ram figure 1.30.2. cpu rewrite mode set/reset flowchart
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 264 figure 1.30.3. shifting to the low speed mode flowchart end start x in oscillating transfer the program to be executed in the low speed mode, to the internal ram. switch the count source of bclk. x in stop. (note 2) jump to transferred control program in ram (subsequent operations are executed by control program in this ram) note 1: for flash memory power supply-off bit to be set to ?? the user needs to write a ??and then a ??to it in succession. when it is not this procedure, it is not enacted in ?? this is necessary to ensure that no interrupt or dma transfer will be executed during the interval. note 2: before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. wait time until the internal circuit stabilizes (set nop instruction about twice) set flash memory power supply-off bit to ? set flash memory power supply-off bit to ? (by writing ??and then ??in succession)(note 1) *1 *1 program in rom program in ram process of low speed mode wait until the x in has stabilized switch the count source of bclk (note 2)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 265 precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during cpu rewrite mode, set the main clock frequency as shown below using the main clock division register (address 000c 16 ): 6.25 mhz or less when wait bit (bit 2 at address 0005 16 ) = 0 (without internal access wait state) 12.5 mhz or less when wait bit (bit 2 at address 0005 16 ) = 1 (with internal access wait state) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use the address match interrupt cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory. if interrupts have their vector in the variable vector table, they can be _______ used by transferring the vector into the ram area. the nmi and watchdog timer interrupts each can be used to change the flash memorys operation mode forcibly to read array mode upon occurrence of _______ the interrupt. since the rewrite operation is halted when the nmi and watchdog timer interrupts occur, the erase/program operation needs to be performed over again. disabling erase or rewrite operations for address fc000 16 to address fffff 16 in the user rom block disables these operations for all subsequent blocks as well. therefore, it is recommended to rewrite this block in the standard serial i/o mode. (4) reset reset input is always accepted. (5) access disable write cpu rewrite mode select bit, flash memory power supply-off bit and user rom area select bit in an area other than the internal flash memory. (6) how to access for cpu rewrite mode select bit, lock bit disable bit, and flash memory power supply-off bit to be set to 1, the user needs to write a 0 and then a 1 to it in succession. when it is not this procedure, it is not enacted in 1. this is necessary to ensure that no interrupt or dma transfer will be executed during the interval.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 266 command page program clear status register read array read status register x x x x (note 3) first bus cycle second bus cycle third bus cycle ff 16 70 16 50 16 41 16 write write write write xsrd read write lock bit program x 77 16 write ba d0 16 write erase all unlock block x a7 16 write x d0 16 write wa1 wd1 write (note 2) wa0 (note 3) wd0 (note 3) block erase x 20 16 write d0 16 write ba (note 4) read lock bit status x 71 16 write ba d 6 read (note 5) mode address mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) data (d 0 to d 7 ) (note 6) note 1: when a software command is input, the high-order byte of data (d 8 to d 15 ) is ignored. note 2: srd = status register data note 3: wa = write address, wd = write data wa and wd must be set sequentially from 00 16 to fe 16 (byte address; however, an even address). the page size is 256 bytes. note 4: ba = block address (enter the maximum address of each block that is an even address.) note 5: d 6 corresponds to the block lock status. block not locked when d 6 = 1, block locked when d 6 = 0. note 6: x denotes a given address in the user rom area (that is an even address). software commands table 1.30.1 lists the software commands available with the m16c/62a (flash memory version). after setting the cpu rewrite mode select bit to 1, write a software command to specify an erase or program operation. note that when entering a software command, the upper byte (d 8 to d 15 ) is ignored. the content of each software command is explained below. table 1.30.1. list of software commands (cpu rewrite mode) read array command (ff 16 ) the read array mode is entered by writing the command code ff 16 in the first bus cycle. when an even address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 Cd 15 ), 16 bits at a time. the read array mode is retained intact until another command is written. read status register command (70 16 ) when the command code 70 16 is written in the first bus cycle, the content of the status register is read out at the data bus (d 0 Cd 7 ) by a read in the second bus cycle. the status register is explained in the next section. clear status register command (50 16 ) this command is used to clear the bits sr3 to 5 of the status register after they have been set. these bits indicate that operation has ended in an error. to use this command, write the command code 50 16 in the first bus cycle.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 267 n = fe 16 start write 41 16 n = 0 write address n and data n ry/by status flag = 1? check full status page program completed n = n + 2 no yes no yes figure 1.30.4. page program flowchart page program command (41 16 ) page program allows for high-speed programming in units of 256 bytes. page program operation starts when the command code 41 16 is written in the first bus cycle. in the second bus cycle through the 129th bus cycle, the write data is sequentially written 16 bits at a time. at this time, the addresses a 0 -a 7 need to be incremented by 2 from 00 16 to fe 16 . when the system finishes loading the data, it starts an auto write operation (data program and verify operation). whether the auto write operation is completed can be confirmed by reading the status register or the flash memory control register 0. at the same time the auto write operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto write operation starts and is returned to 1 upon completion of the auto write operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. ____ the ry/by status flag of the flash memory control register 0 is 0 during auto write operation and 1 when the auto write operation is completed as is the status register bit 7. after the auto write operation is completed, the status register can be read out to know the result of the auto write operation. for details, refer to the section where the status register is detailed. figure 1.30.4 shows an example of a page program flowchart. each block of the flash memory can be write protected by using a lock bit. for details, refer to the section where the data protect function is detailed. additional writes to the already programmed pages are prohibited.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 268 write 20 16 write d0 16 block address check full status check block erase completed start ry/by status flag = 1? no yes figure 1.30.5. block erase flowchart block erase command (20 16 /d0 16 ) by writing the command code 20 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system initiates an auto erase (erase and erase verify) operation. whether the auto erase operation is completed can be confirmed by reading the status register or the flash memory control register 0. at the same time the auto erase operation starts, the read status register mode is automatically entered, so the content of the status register can be read out. the status register bit 7 (sr7) is set to 0 at the same time the auto erase operation starts and is returned to 1 upon completion of the auto erase operation. in this case, the read status register mode remains active until the read array command (ff 16 ) or read lock bit status command (71 16 ) is written or the flash memory is reset using its reset bit. ____ the ry/by status flag of the flash memory control register 0 is 0 during auto erase operation and 1 when the auto erase operation is completed as is the status register bit 7. after the auto erase operation is completed, the status register can be read out to know the result of the auto erase operation. for details, refer to the section where the status register is detailed. figure 1.30.5 shows an example of a block erase flowchart. each block of the flash memory can be protected against erasure by using a lock bit. for details, refer to the section where the data protect function is detailed.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 269 write 77 16 write d0 16 block address sr4 = 0? no lock bit program completed lock bit program in error yes start ry/by status flag = 1? no yes erase all unlock blocks command (a7 16 /d0 16 ) by writing the command code a7 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows, the system starts erasing blocks successively. whether the erase all unlock blocks command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for block erase. also, the status register can be read out to know the result of the auto erase operation. when the lock bit disable bit of the flash memory control register 0 = 1, all blocks are erased no matter how the lock bit is set. on the other hand, when the lock bit disable bit = 0, the function of the lock bit is effective and only nonlocked blocks (where lock bit data = 1) are erased. lock bit program command (77 16 /d0 16 ) by writing the command code 77 16 in the first bus cycle and the confirmation command code d0 16 in the second bus cycle that follows to the block address of a flash memory block, the system sets the lock bit for the specified block to 0 (locked). figure 1.30.6 shows an example of a lock bit program flowchart. the status of the lock bit (lock bit data) can be read out by a read lock bit status command. whether the lock bit program command is terminated can be confirmed by reading the status register or the flash memory control register 0, in the same way as for page program. for details about the function of the lock bit and how to reset the lock bit, refer to the section where the data protect function is detailed. figure 1.30.6. lock bit program flowchart
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 270 write 71 16 enter block address d6 = 0? no blocks locked blocks not locked yes start read lock bit status command (71 16 ) by writing the command code 71 16 in the first bus cycle and then the block address of a flash memory block in the second bus cycle that follows, the system reads out the status of the lock bit of the specified block on to the data (d6). figure 1.30.7 shows an example of a read lock bit program flowchart. figure 1.30.7. read lock bit status flowchart
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 271 data protect function (block lock) each block in figure 1.29.3 has a nonvolatile lock bit to specify that the block be protected (locked) against erase/write. the lock bit program command is used to set the lock bit to 0 (locked). the lock bit of each block can be read out using the read lock bit status command. whether block lock is enabled or disabled is determined by the status of the lock bit and how the flash memory control register 0s lock bit disable bit is set. (1) when the lock bit disable bit = 0, a specified block can be locked or unlocked by the lock bit status (lock bit data). blocks whose lock bit data = 0 are locked, so they are disabled against erase/write. on the other hand, the blocks whose lock bit data = 1 are not locked, so they are enabled for erase/ write. (2) when the lock bit disable bit = 1, all blocks are nonlocked regardless of the lock bit data, so they are enabled for erase/write. in this case, the lock bit data that is 0 (locked) is set to 1 (nonlocked) after erasure, so that the lock bit-actuated lock is removed. status register the status register indicates the operating status of the flash memory and whether an erase or program operation has terminated normally or in an error. the content of this register can be read out by only writing the read status register command (70 16 ). table 1.30.2 details the status register. the status register is cleared by writing the clear status register command (50 16 ). after a reset, the status register is set to 80 16 . each bit in this register is explained below. write state machine (wsm) status (sr7) after power-on, the write state machine (wsm) status is set to 1. the write state machine (wsm) status indicates the operating status of the device, as for output on the ____ ry/by pin. this status bit is set to 0 during auto write or auto erase operation and is set to 1 upon completion of these operations. erase status (sr5) the erase status informs the operating status of auto erase operation to the cpu. when an erase error occurs, it is set to 1. the erase status is reset to 0 when cleared.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 272 each bit of srd sr4 (bit4) sr5 (bit5) sr7 (bit7) sr6 (bit6) status name definition sr1 (bit1) sr2 (bit2) sr3 (bit3) sr0 (bit0) "1" "0" program status erase status write state machine (wsm) status reserved reserved reserved block status after program reserved ready busy terminated in error terminated in error terminated in error terminated normally terminated normally terminated normally - - - - - - - - program status (sr4) the program status informs the operating status of auto write operation to the cpu. when a write error occurs, it is set to 1. the program status is reset to 0 when cleared. when an erase command is in error (which occurs if the command entered after the block erase command (20 16 ) is not the confirmation command (d0 16 ), both the program status and erase status (sr5) are set to 1. when the program status or erase status = 1, the following commands entered by command write are not accepted. also, in one of the following cases, both sr4 and sr5 are set to 1 (command sequence error): (1) when the valid command is not entered correctly (2) when the data entered in the second bus cycle of lock bit program (77 16 /d0 16 ), block erase (20 16 /d0 16 ), or erase all unlock blocks (a7 16 /d0 16 ) is not the d0 16 or ff 16 . however, if ff 16 is entered, read array is assumed and the command that has been set up in the first bus cycle is canceled. block status after program (sr3) if excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), 1 is set for the program status after-program at the end of the page write operation. in other words, when writing ends successfully, 80 16 is output; when writing fails, 90 16 is output; and when excessive data is written, 88 16 is output. table 1.30.2. definition of each bit in status register
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer cpu rewrite mode (flash memory version) 273 read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands. full status check by performing full status check, it is possible to know the execution results of erase and program operations. figure 1.30.8 shows a full status check flowchart and the action to be taken when each error occurs. figure 1.30.8. full status check flowchart and remedial procedure for errors
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer functions to inhibit rewriting flash memory version (flash memory version) 274 symbol address when reset romcp 0ffffff 16 ff 16 rom code protect level 2 set bit (note 1, 2) 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect control address bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 00: protect removed 01: protect set bit effective 10: protect set bit effective 11: protect set bit effective 00: protect enabled 01: protect enabled 10: protect enabled 11: protect disabled rom code protect reset bit (note 3) rom code protect level 1 set bit (note 1) romcp2 romcr romcp1 b3 b2 b5 b4 b7 b6 note 1: when rom code protect is turned on, the on-chip flash memory is protected against readout or modification in parallel input/output mode. note 2: when rom code protect level 2 is turned on, rom code readout by a shipment inspection lsi tester, etc. also is inhibited. note 3: the rom code protect reset bits can be used to turn off rom code protect level 1 and rom code protect level 2. however, since these bits cannot be changed in parallel input/ output mode, they need to be rewritten in serial input/output or some other mode. reserved bit always set this bit to 1. 1 1 functions to inhibit rewriting flash memory version to prevent the contents of the flash memory version from being read out or rewritten easily, the device incorporates a rom code protect function for use in parallel i/o mode and an id code check function for use in standard serial i/o mode. rom code protect function the rom code protect function reading out or modifying the contents of the flash memory version by using the rom code protect control address (0ffffff 16 ) during parallel i/o mode. figure 1.31.1 shows the rom code protect control address (0ffffff 16 ). (this address exists in the user rom area.) if one of the pair of rom code protect bits is set to 0, rom code protect is turned on, so that the contents of the flash memory version are protected against readout and modification. rom code protect is imple- mented in two levels. if level 2 is selected, the flash memory is protected even against readout by a shipment inspection lsi tester, etc. when an attempt is made to select both level 1 and level 2, level 2 is selected by default. if both of the two rom code protect reset bits are set to 00, rom code protect is turned off, so that the contents of the flash memory version can be read out or modified. once rom code protect is turned on, the contents of the rom code protect reset bits cannot be modified in parallel i/o mode. use the serial i/ o or some other mode to rewrite the contents of the rom code protect reset bits. figure 1.31.1. rom code protect control address
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer functions to inhibit rewriting flash memory version (flash memory version) 275 id code check function use this function in standard serial i/o mode. when the contents of the flash memory are not blank, the id code sent from the peripheral unit is compared with the id code written in the flash memory to see if they match. if the id codes do not match, the commands sent from the peripheral unit are not accepted. the id code consists of 8-bit data, the areas of which, beginning with the first byte, are 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 , and 0fffffb 16 . write a program which has had the id code preset at these addresses to the flash memory. figure 1.31.2. id code store addresses reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix parallel i/o mode (flash memory version) 276 parallel i/o mode in this mode, the m16c/80 (flash memory version) operates in a manner similar to the flash memory m5m29fb/t800 from mitsubishi. since there are some differences with regard to the functions not avail- able with the microcomputer and matters related to memory capacity, the m16c/80 cannot be programed by a programer for the flash memory. use an exclusive programer supporting m16c/80 (flash memory version). refer to the instruction manual of each programer maker for the details of use. user rom and boot rom areas in parallel i/o mode, the user rom and boot rom areas shown in figure 1.29.3 can be rewritten. both areas of flash memory can be operated on in the same way. program and block erase operations can be performed in the user rom area. the user rom area and its blocks are shown in figure 1.29.3. the boot rom area is 8 kbytes in size. in parallel i/o mode, it is located at addresses 0ffe000 16 through 0ffffff 16 . make sure program and block erase operations are always performed within this address range. (access to any location outside this address range is prohibited.) in the boot rom area, an erase block operation is applied to only one 8 kbyte block. the boot rom area has had a standard serial i/o mode control program stored in it when shipped from the mitsubishi factory. therefore, using the device in standard serial input/output mode, you do not need to write to the boot rom area.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 277 pin functions (flash memory standard serial i/o mode) pin description v cc ,v ss apply 4.2v to 5.5v to vcc pin and 0 v to vss pin. cnv ss connect to vcc pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out byte connect this pin to vcc or vss. av cc , av ss v ref connect avss to vss and avcc to vcc, respectively. enter the reference voltage for a-d converter from this pin. p0 0 to p0 7 input "h" or "l" level signal or open. p1 0 to p1 7 input "h" or "l" level signal or open. p2 0 to p2 7 input "h" or "l" level signal or open. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 7 input "h" or "l" level signal or open. p5 1 to p5 4, p5 6, p5 7 input "h" or "l" level signal or open. p5 0 input "h" level signal. p5 5 input "l" level signal. p6 0 to p6 3 input "h" or "l" level signal or open. p6 4 p6 5 p6 6 serial data input pin p6 7 serial data output pin p7 0 to p7 7 input "h" or "l" level signal or open. p8 0 to p8 4 , p8 6 , p8 7 input "h" or "l" level signal or open. p9 0 to p9 7 input "h" or "l" level signal or open. p10 0 to p10 7 input "h" or "l" level signal or open. name power input cnv ss reset input clock input clock output byte analog power supply input reference voltage input input port p0 input port p1 input port p2 input port p3 input port p4 input port p5 ce input epm input input port p6 busy output sclk input rxd input txd output input port p7 input port p8 input port p9 input port p10 i/o i i i o i i i i i i i i i i i o i i o i i i i p8 5 nmi input i connect this pin to vcc. i p11 0 to p11 4 input "h" or "l" level signal or open. input port p11 i p12 0 to p12 7 input "h" or "l" level signal or open. input port p12 i p13 0 to p13 7 input "h" or "l" level signal or open. input port p13 i p14 0 to p14 6 input "h" or "l" level signal or open. input port p14 i p15 0 to p15 7 input "h" or "l" level signal or open. input port p15 i standard serial mode 1: busy signal output pin standard serial mode 2: monitors the program operation check standard serial mode 1: serial clock input pin standard serial mode 2: input "l" level signal.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 278 figure 1.32.1. pin connections for serial i/o mode 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 p14 6 p14 5 p14 4 p14 3 p14 1 p14 2 p14 0 byte cnv ss p8 7 /x cin p8 6 /x cout x out v ss x in v cc p8 0 /ta 4out /u p7 7 /ta 3in p7 6 /ta 3out p7 4 /ta 2out /w p7 2 /clk 2 /ta 1out /v p7 1 /r x d 2 /scl 2 /ta 0in /tb 5in reset p8 5 /nmi p8 4 /int 2 p8 3 /int 1 p8 2 /int 0 p8 1 /ta 4in /u p7 5 /ta 2in /w p7 3 /cts 2 /rts 2 /ta 1in /v 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 p7 0 /t x d 2 /sda 2 /ta 0out p6 7 /t x d 1 v cc p6 6 /r x d 1 v ss p6 5 /clk 1 p6 3 /t x d 0 p6 2 /r x d 0 p6 1 /clk 0 p13 7 p13 6 p13 5 p13 4 p13 3 v ss p13 2 v cc p13 1 p13 0 p5 3 /bclk/ale/clk out p12 7 p12 6 p12 5 p6 4 /cts 1 /rts 1 /cts 0 /clks 1 p6 0 /cts 0 /rts 0 p5 6 /ale/ras p5 5 /hold p5 4 /hlda/ale p5 2 /rd/dw p5 1 /wrh/bhe/cash p5 0 /wrl/wr/casl p4 7 /cs0/a 23 p4 6 /cs1/a 22 p4 5 /cs2/a 21 p4 4 /cs3/a 20 (ma12) p4 3 /a 19 (ma11) v cc p4 2 /a 18 (ma10) v ss p4 1 /a 17 (ma9) p4 0 /a 16 (ma8) p3 7 /a 15 (ma7)(/d 15 ) p3 6 /a 14 (ma6)(/d 14 ) p3 5 /a 13 (ma5)(/d 13 ) p3 4 /a 12 (ma4)(/d 12 ) p3 3 /a 11 (ma3)(/d 11 ) p3 2 /a 10 (ma2)(/d 10 ) p3 1 /a 9 (ma1)(/d 9 ) p12 4 p12 3 p12 2 p12 1 p12 0 v cc p3 0 /a 8 (ma0)(/d 8 ) p2 7 /a 7 (/d 7 ) p2 6 /a 6 (/d 6 ) p2 5 /a 5 (/d 5 ) p2 4 /a 4 (/d 4 ) p2 3 /a 3 (/d 3 ) p2 2 /a 2 (/d 2 ) p2 1 /a 1 (/d 1 ) p2 0 /a 0 (/d 0 ) v ss p1 4 /d 12 p1 3 /d 11 p1 2 /d 10 p1 1 /d 9 p1 5 /d 13 /int3 p1 6 /d 14 /int4 p1 7 /d 15 /int5 p1 0 /d 8 p0 7 /d 7 p0 6 /d 6 p0 5 /d 5 p0 4 /d 4 p11 4 p11 3 p11 2 p11 1 p11 0 p0 3 /d 3 p0 2 /d 2 p0 1 /d 1 p0 0 /d 0 p15 7 p15 6 p15 5 p15 4 p15 3 p15 2 p15 1 v ss p15 0 v cc p10 3 /an 3 p10 2 /an 2 p10 1 /an 1 av ss p10 0 /an 0 v ref av cc p10 7 /an 7 /ki3 p10 6 /an 6 /ki2 p10 5 /an 5 /ki1 p10 4 /an 4 /ki0 p9 7 /ad trg /r x d 4 / scl 4 /stxd 4 73 74 75 76 77 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 78 p5 7 /rdy 12 3 4 7 6 8 9 10111213141516 1718192021222324252627282930 5 31 32 33 34 35 36 m16c/80(144-pin) group flash memory version (144p6q) cnv ss reset epm ce v cc v ss txd rxd sclk busy signal value cnvss vcc epm vss reset vss >> vcc ce vcc mode setting connect oscillation circuit p9 6 /anex 1 /t x d 4 /sda 4 /srxd 4 p9 5 /anex 0 /clk 4 p9 2 /tb 2in /t x d 3 /sda 3 /srxd 3 p9 1 /tb 1in /r x d 3 /scl 3 /stxd 3 p9 0 /tb 0in /clk3 p9 4 /da 1 /tb 4in /cts 4 /rts 4 /ss 4 p9 3 /da 0 /tb 3in /cts 3 /rts 3 /ss 3
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode (flash memory version) 279 standard serial i/o mode the standard serial i/o mode inputs and outputs the software commands, addresses and data needed to operate (read, program, erase, etc.) the internal flash memory. this i/o is serial. there are actually two standard serial i/o modes: mode 1, which is clock synchronized, and mode 2, which is asynchronized. both modes require a purpose-specific peripheral unit. the standard serial i/o mode is different from the parallel i/o mode in that the cpu controls flash memory rewrite (uses the cpu's rewrite mode), rewrite data input and so forth. it is started when the reset is re- _____ ________ leased, which is done when the p5 0 (ce) pin is "h" level, the p5 5 (epm) pin "l" level and the cnvss pin "h" level. (in the ordinary command mode, set cnvss pin to "l" level.) this control program is written in the boot rom area when the product is shipped from mitsubishi. accord- ingly, make note of the fact that the standard serial i/o mode cannot be used if the boot rom area is rewritten in the parallel i/o mode. figures 1.32.1 and 1.32.2 show the pin connections for the standard serial i/o mode. serial data i/o uses uart1 and transfers the data serially in 8-bit units. standard serial i/ o switches between mode 1 (clock synchronized) and mode 2 (clock asynchronized) according to the level of clk 1 pin when the reset is released. to use standard serial i/o mode 1 (clock synchronized), set the clk 1 pin to "h" level and release the reset. the operation uses the four uart1 pins clk 1 , rxd 1 , txd 1 and rts 1 (busy). the clk 1 pin is the transfer clock input pin through which an external transfer clock is input. the txd 1 pin is for cmos output. the rts 1 (busy) pin outputs an "l" level when ready for reception and an "h" level when reception starts. to use standard serial i/o mode 2 (clock asynchronized), set the clk 1 pin to "l" level and release the reset. the operation uses the two uart1 pins rxd 1 and txd 1 . in the standard serial i/o mode, only the user rom area indicated in figure 1.32.19 can be rewritten. the boot rom cannot. in the standard serial i/o mode, a 7-byte id code is used. when there is data in the flash memory, com- mands sent from the peripheral unit (programmer) are not accepted unless the id code matches.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 280 overview of standard serial i/o mode 1 (clock synchronized) in standard serial i/o mode 1, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 4-wire clock-synchronized serial i/o (uart1). standard serial i/o mode 1 is engaged by releasing the reset with the p5 6 (clk 1 ) pin "h" level. in reception, software commands, addresses and program data are synchronized with the rise of the trans- fer clock that is input to the clk 1 pin, and are then input to the mcu via the rxd 1 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock, and output from the txd 1 pin. the txd 1 pin is for cmos output. transfer is in 8-bit units with lsb first. when busy, such as during transmission, reception, erasing or program execution, the rts 1 (busy) pin is "h" level. accordingly, always start the next transfer after the rst 1 (busy) pin is "l" level. also, data and status registers in memory can be read after inputting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained software commands, status registers, etc.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 281 software commands table 1.32.1 lists software commands. in the standard serial i/o mode 1, erase operations, programs and reading are controlled by transferring software commands via the rxd 1 pin. software commands are explained here below. table 1.32.1. software commands (standard serial i/o mode 1) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lock bit status 8 lock bit program 9 lock bit enable 10 lock bit disable 11 code processing function 12 download function 13 version data output function 14 boot rom area output function 15 read check data address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (middle) address (low) size (low) version data output address (middle) check data (low) address (high) address (high) address (high) srd1 output address (high) address (high) address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 lock bit data output d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 77 16 7a 16 75 16 f5 16 fa 16 fb 16 fc 16 fd 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable 1st byte transfer note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register 1 data. note 3: all commands can be accepted when the flash memory is totally blank.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 282 page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.32.2. timing for page read read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.32.3. timing for reading the status register data0 data255 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 ff 16 (m16c reception data) (m16c transmit data) srd output srd1 output clk1 rxd1 txd1 rts1(busy) 70 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 283 clear status register command this command clears the bits (sr3Csr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. when the clear status register operation ends, the rts 1 (busy) signal changes from the h to the l level. figure 1.32.4. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts 1 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. each block can be write-protected with the lock bit. for more information, see the section on the data protection function. additional writing is not allowed with already programmed pages. figure 1.32.5. timing for the page program clk1 rxd1 txd1 rts1(busy) 50 16 (m16c reception data) (m16c transmit data) clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 284 block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when block erasing ends, the rts 1 (busy) signal changes from the h to the l level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.32.6. timing for block erasing a 8 to a 15 a 16 to a 23 20 16 d0 16 clk1 rxd1 txd1 rts1(busy) (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 285 erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts 1 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.32.7. timing for erasing all unlocked blocks lock bit program command this command writes 0 (lock) for the lock bit of the specified block. execute the lock bit program command as explained here following. (1) transfer the 77 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, 0 is written for the lock bit of the specified block. write the highest address of the specified block for addresses a 8 to a 23 . when writing ends, the rts 1 (busy) signal changes from the h to the l level. lock bit status can be read with the read lock bit status command. for information on the lock bit function, reset proce- dure and so on, see the section on the data protection function. figure 1.32.8. timing for the lock bit program clk1 rxd1 txd1 rts1(busy) a7 16 d0 16 (m16c reception data) (m16c transmit data) clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 77 16 d0 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 286 lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable com- mand. the command code 7a 16 is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) transfer the 71 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. the 6th bit (d6) of output data is the lock bit data. write the highest address of the specified block for addresses a 8 to a 23 . figure 1.32.9. timing for reading lock bit status figure 1.32.10. timing for enabling the lock bit clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 71 16 dq6 (m16c reception data) (m16c transmit data) 7a 16 clk1 rxd1 txd1 rts1(busy) (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 287 lock bit disable command this command disables the lock bit. the command code 75 16 is sent with the 1st byte of the serial transmission. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, 0 (locked) lock bit data is set to 1 (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. figure 1.32.11. timing for disabling the lock bit download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. figure 1.32.12. timing for download 75 16 clk1 rxd1 txd1 rts1(busy) (m16c reception data) (m16c transmit data) fa 16 program data data size (high) data size (low) check sum clk1 rxd1 txd1 rts1(busy) (m16c reception data) (m16c transmit data) program data
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 288 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.32.13. timing for version information output boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. figure 1.32.14. timing for boot rom area output fb 16 'x' 'v' 'e' 'r' clk1 rxd1 txd1 rts1(busy) (m16c reception data) (m16c transmit data) data0 data255 clk1 rxd1 txd1 rts1(busy) a 8 to a 15 a 16 to a 23 fc 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 289 id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.32.15. timing for the id check id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 and 0fffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.32.16. id code storage addresses id size id1 id7 clk1 rxd1 txd1 rts1(busy) f5 16 df 16 ff 16 0f 16 (m16c reception data) (m16c transmit data) reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 290 read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. the check data is the result of crc operation of write data. figure 1.32.17. timing for the read check data check data (low) clk1 rxd1 txd1 rts1(busy) fd 16 (m16c reception data) (m16c transmit data) check data (high)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 291 data protection (block lock) each of the blocks in figure 1.32.19 have a nonvolatile lock bit that specifies protection (block lock) against erasing/writing. a block is locked (writing 0 for the lock bit) with the lock bit program command. also, the lock bit of any block can be read with the read lock bit status command. block lock disable/enable is determined by the status of the lock bit itself and execution status of the lock bit disable and lock enable bit commands. (1) after the reset has been cancelled and the lock bit enable command executed, the specified block can be locked/unlocked using the lock bit (lock bit data). blocks with a 0 lock bit data are locked and cannot be erased or written in. on the other hand, blocks with a 1 lock bit data are unlocked and can be erased or written in. (2) after the lock bit enable command has been executed, all blocks are unlocked regardless of lock bit data status and can be erased or written in. in this case, lock bit data that was 0 before the block was erased is set to 1 (unlocked) after erasing, therefore the block is actually unlocked with the lock bit. figure 1.32.18. blocks in the user area 0fc0000 16 0fd0000 16 block 6 : 64k byte block 5 : 64k byte 0fe0000 16 block 4 : 64k byte 0ff0000 16 block 3 : 32k byte 0ff8000 16 block 2 : 8k byte 0ffa000 16 block 1 : 8k byte block 0 : 16k byte 0ffc000 16 user rom area 8k byte 0ffe000 16 0ffffff 16 0ffffff 16 boot rom area flash memory start address 0fe0000 16 0fc0000 16 note 1: the boot rom area can be rewritten in only parallel input/output mode. (access to any other areas is inhibited.) note 2: to specify a block, use the maximum address in the block that is an even address. flash memory size 256kbytes 128kbytes
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 292 status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table 1.32.2 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table 1.32.2. status register (srd) write state machine (wsm) status (sr7) the write state machine (wsm) status indicates the operating status of the flash memory. when power is turned on, 1 (ready) is set for it. the bit is set to 0 (busy) during an auto write or auto erase operation, but it is set back to 1 when the operation ends. erase status (sr5) the erase status reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1. when the erase status is cleared, it is set to 0. program status (sr4) the program status reports the operating status of the auto write operation. if a write error occurs, it is set to 1. when the program status is cleared, it is set to 0. program status after program (sr3) if excessive data is written (phenomenon whereby the memory cell becomes depressed which results in data not being read correctly), 1 is set for the program status after-program at the end of the page write operation. in other words, when writing ends successfully, 80 16 is output; when writing fails, 90 16 is output; and when excessive data is written, 88 16 is output. if 1 is written for any of the sr5, sr4 or sr3 bits, the page program, block erase, erase all unlocked blocks and lock bit program commands are not accepted. before executing these commands, execute the clear status register command (50 16 ) and clear the status register. srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) status name write state machine (wsm) status reserved erase status program status block status after program reserved reserved reserved definition "1" "0" ready - terminated in error terminated in error terminated in error - - - busy - terminated normally terminated normally terminated normally - - -
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 293 status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table 1.32.3 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table 1.32.3. status register 1 (srd1) boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" update co mpleted - - match 00 01 10 11 not update - - mismatch normal operation - not verified verification mismatch reserved verified time out -
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 1 (flash memory version) 294 full status check results from executed erase and program operations can be known by running a full status check. figure 1.32.19 shows a flowchart of the full status check and explains how to remedy errors which occur. read status register sr4=1 and sr5 =1 ? no command sequence error yes sr5=0? yes block erase error no sr4=0? yes program error (page or lock bit) no sr3=0? yes program error (block) no end (block erase, program) execute the clear status register command (50 16 ) to clear the status register. try performing the operation one more time after confirming that the command is entered correctly. should a block erase error occur, the block in error cannot be used. execute the read lock bit status command (71 16 ) to see if the block is locked. after removing lock, execute write operation in the same way. if the error still occurs, the page in error cannot be used. after erasing the block in error, execute write operation one more time. if the same error still occurs, the block in error cannot be used. note: when one of sr5 to sr3 is set to 1, none of the page program, block erase, erase all unlock blocks and lock bit program commands is accepted. execute the clear status register command (50 16 ) before executing these commands. figure 1.32.19. full status check flowchart and remedial procedure for errors example circuit application for the standard serial i/o mode 1 the below figure shows a circuit application for the standard serial i/o mode 1. control pins will vary according to the peripheral unit (programmer), therefore see the peripheral unit (programmer) manual for more information. figure 1.32.20. example circuit application for the standard serial i/o mode 1 clock input busy output data input data output (1) control pins and external circuitry will vary according to peripheral unit (programmer). for more information, see the peripheral unit (programmer) manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. rts1(busy) clk1 r x d1 t x d1 cnvss p5 0 (ce) p5 5 (epm) nmi m16c/80 flash memory version
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 295 overview of standard serial i/o mode 2 (clock asynchronized) in standard serial i/o mode 2, software commands, addresses and data are input and output between the mcu and peripheral units (serial programer, etc.) using 2-wire clock-asynchronized serial i/o (uart1). standard serial i/o mode 2 is engaged by releasing the reset with the p6 5 (clk 1 ) pin "l" level. the txd 1 pin is for cmos output. data transfer is in 8-bit units with lsb first, 1 stop bit and parity off. after the reset is released, connections can be established at 9,600 bps when initial communications (fig- ure 1.32.21) are made with a peripheral unit. however, this requires a main clock with a minimum 2 mhz input oscillation frequency. baud rate can also be changed from 9,600 bps to 19,200, 38,400, 57,600 or 115,200 bps by executing software commands. however, communication errors may occur because of the oscillation frequency of the main clock. if errors occur, change the main clock's oscillation frequency and the baud rate. after executing commands from a peripheral unit that requires time to erase and write data, as with erase and program commands, allow a sufficient time interval or execute the read status command and check how processing ended, before executing the next command. data and status registers in memory can be read after transmitting software commands. status, such as the operating state of the flash memory or whether a program or erase operation ended successfully or not, can be checked by reading the status register. here following are explained initial communications with peripheral units, how frequency is identified and software commands. initial communications with peripheral units after the reset is released, the bit rate generator is adjusted to 9,600 bps to match the oscillation fre- quency of the main clock, by sending the code as prescribed by the protocol for initial communications with peripheral units (figure 1.32.21). (1) transmit "00 16 " from a peripheral unit 16 times. (the mcu with internal flash memory sets the bit rate generator so that "00 16 " can be successfully received.) (2) the mcu with internal flash memory outputs the "b0 16 " check code and initial communications end successfully * 1 . initial communications must be transmitted at a speed of 9,600 bps and a transfer interval of a minimum 15 ms. also, the baud rate at the end of initial communications is 9,600 bps. *1. if the peripheral unit cannot receive "b0 16 " successfully, change the oscillation frequency of the main clock. figure 1.32.21. peripheral unit and initial communication mcu with internal flash memory peripheral unit (1) transfer "00 16 " 16 times at least 15ms transfer interval 1st 2nd 15 th 16th (2) transfer check code "b0 16 " "00 16 " "00 16 " "00 16 " "b0 16 " "00 16 " reset the bit rate generator setting completes (9600bps)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 296 how frequency is identified when "00 16 " data is received 16 times from a peripheral unit at a baud rate of 9,600 bps, the value of the bit rate generator is set to match the operating frequency (2 - 20 mhz). the highest speed is taken from the first 8 transmissions and the lowest from the last 8. these values are then used to calculate the bit rate generator value for a baud rate of 9,600 bps. baud rate cannot be attained with some operating frequencies. table 1.32.4 gives the operation fre- quency and the baud rate that can be attained for. table 1.32.4 operation frequency and the baud rate operation frequency (mh z ) baud rate 9,600bps baud rate 19,200bps baud rate 38,400bps baud rate 57,600bps 20mhz 16mh z 12mh z 11mh z 10mh z 8mh z 7.3728mh z 6mh z 5mh z 4.5mh z 4.194304mh z 4mh z 3.58mh z 3mh z 2mh z : communications possible ?: communications not possible baud rate 115,200bps ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 297 software commands table 1.32.5 lists software commands. in the standard serial i/o mode 2, erase operations, programs and reading are controlled by transferring software commands via the rxd 1 pin. standard serial i/o mode 2 adds five transmission speed commands - 9,600, 19,200, 38,400, 57,600 and 115,200 bps - to the soft- ware commands of standard serial i/o mode 1. software commands are explained here below. table 1.32.5. software commands (standard serial i/o mode 2) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 block erase 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lock bit status 8 lock bit program 9 lock bit enable 10 lock bit disable 11 code processing function 12 download function 13 version data output function 14 boot rom area output function 15 read check data 16 baud rate 9600 17 baud rate 19200 18 baud rate 38400 19 baud rate 57600 20 baud rate 115200 address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (middle) address (low) size (low) version data output address (middle) check data (low) b0 16 b1 16 b2 16 b3 16 b4 16 address (high) address (high) address (high) srd1 output address (high) address (high) address (middle) size (high) version data output address (high) check data (high) data output data input d0 16 lock bit data output d0 16 address (high) check- sum version data output data output data output data input id size data input version data output data output data output data input id1 to required number of times version data output data output data output to 259th byte data input to 259th byte to id7 version data output to 9th byte data output to 259th byte ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 77 16 7a 16 75 16 f5 16 fa 16 fb 16 fc 16 fd 16 b0 16 b1 16 b2 16 b3 16 b4 16 when id is not verified not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable not acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable not acceptable acceptable acceptable acceptable acceptable acceptable 1st byte transfer note 1: shading indicates transfer from flash memory microcomputer to peripheral unit. all other data is trans- ferred from the peripheral unit to the flash memory microcomputer. note 2: srd refers to status register data. srd1 refers to status register 1 data. note 3: all commands can be accepted when the flash memory is totally blank.
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 298 rxd1 txd1 50 16 (m16c reception data) (m16c transmit data) page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) transfer the ff 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. figure 1.32.22. timing for page read read status register command this command reads status information. when the 70 16 command code is sent with the 1st byte, the contents of the status register (srd) specified with the 2nd byte and the contents of status register 1 (srd1) specified with the 3rd byte are read. figure 1.32.23. timing for reading the status register clear status register command this command clears the bits (sr3Csr5) which are set when the status register operation ends in error. when the 50 16 command code is sent with the 1st byte, the aforementioned bits are cleared. figure 1.32.24. timing for clearing the status register data0 data255 rxd1 txd1 a 8 to a 15 a 16 to a 23 ff 16 (m16c reception data) (m16c transmit data) srd output srd1 output rxd1 txd1 70 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 299 page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) transfer the 41 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. the result of the page program can be known by reading the status register. for more information, see the section on the status register. each block can be write-protected with the lock bit. for more information, see the section on the data protection function. additional writing is not allowed with already programmed pages. figure 1.32.25. timing for the page program rxd1 txd1 a 8 to a 15 a 16 to a 23 41 16 data0 data255 (m16c reception data) (m16c transmit data) block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) transfer the 20 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure 1.32.26. timing for block erasing a 8 to a 15 a 16 to a 23 20 16 d0 16 rxd1 txd1 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 300 erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) transfer the a7 16 command code with the 1st byte. (2) transfer the verify command code d0 16 with the 2nd byte. with the verify command code, the erase operation will start and continue for all blocks in the flash memory. the result of the erase operation can be known by reading the status register. each block can be erase- protected with the lock bit. for more information, see the section on the data protection function. figure 1.32.27. timing for erasing all unlocked blocks lock bit program command this command writes 0 (lock) for the lock bit of the specified block. execute the lock bit program command as explained here following. (1) transfer the 77 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) transfer the verify command code d0 16 with the 4th byte. with the verify command code, 0 is written for the lock bit of the specified block. write the highest address of the specified block for addresses a 8 to a 23 . lock bit status can be read with the read lock bit status command. for information on the lock bit function, reset procedure and so on, see the section on the data protection function. figure 1.32.28. timing for the lock bit program rxd1 txd1 a7 16 d0 16 (m16c reception data) (m16c transmit data) rxd1 txd1 a 8 to a 15 a 16 to a 23 77 16 d0 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 301 lock bit enable command this command enables the lock bit in blocks whose bit was disabled with the lock bit disable com- mand. the command code 7a 16 is sent with the 1st byte of the serial transmission. this command only enables the lock bit function; it does not set the lock bit itself. read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) transfer the 71 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) the lock bit data of the specified block is output with the 4th byte. write the highest address of the specified block for addresses a 8 to a 23 . figure 1.32.29. timing for reading lock bit status figure 1.32.30. timing for enabling the lock bit rxd1 txd1 a 8 to a 15 a 16 to a 23 71 16 dq6 (m16c reception data) (m16c transmit data) 7a 16 rxd1 txd1 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 302 lock bit disable command this command disables the lock bit. the command code 75 16 is sent with the 1st byte of the serial transmission. this command only disables the lock bit function; it does not set the lock bit itself. however, if an erase command is executed after executing the lock bit disable command, 0 (locked) lock bit data is set to 1 (unlocked) after the erase operation ends. in any case, after the reset is cancelled, the lock bit is enabled. fa 16 program data data size (high) data size (low) check sum rxd1 txd1 (m16c reception data) (m16c transmit data) program data figure 1.32.31. timing for disabling the lock bit download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) transfer the fa 16 command code with the 1st byte. (2) transfer the program size with the 2nd and 3rd bytes. (3) transfer the check sum with the 4th byte. the check sum is added to all data sent with the 5th byte onward. (4) the program to execute is sent with the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. 75 16 rxd1 txd1 (m16c reception data) (m16c transmit data) figure 1.32.32. timing for download
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 303 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) transfer the fb 16 command code with the 1st byte. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure 1.32.33. timing for version information output boot rom area output command this command outputs the control program stored in the boot rom area in one page blocks (256 bytes). execute the boot rom area output command as explained here following. (1) transfer the fc 16 command code with the 1st byte. (2) transfer addresses a 8 to a 15 and a 16 to a 23 with the 2nd and 3rd bytes respectively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. figure 1.32.34. timing for boot rom area output fb 16 'x' 'v' 'e' 'r' rxd1 txd1 (m16c reception data) (m16c transmit data) data0 data255 rxd1 txd1 a 8 to a 15 a 16 to a 23 fc 16 (m16c reception data) (m16c transmit data)
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 304 id check this command checks the id code. execute the boot id check command as explained here following. (1) transfer the f5 16 command code with the 1st byte. (2) transfer addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code with the 2nd, 3rd and 4th bytes respectively. (3) transfer the number of data sets of the id code with the 5th byte. (4) the id code is sent with the 6th byte onward, starting with the 1st byte of the code. figure 1.32.35. timing for the id check id code when the flash memory is not blank, the id code sent from the peripheral units and the id code written in the flash memory are compared to see if they match. if the codes do not match, the command sent from the peripheral units is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0ffffdf 16 , 0ffffe3 16 , 0ffffeb 16 , 0ffffef 16 , 0fffff3 16 , 0fffff7 16 and 0fffffb 16 . write a program into the flash memory, which already has the id code set for these addresses. figure 1.32.36. id code storage addresses id size id1 id7 rxd1 txd1 f5 16 df 16 ff 16 0f 16 (m16c reception data) (m16c transmit data) reset vector watchdog timer vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 nmi vector 0fffffc 16 to 0ffffff 16 0fffff8 16 to 0fffffb 16 0fffff4 16 to 0fffff7 16 0fffff0 16 to 0fffff3 16 0ffffec 16 to 0ffffef 16 0ffffe8 16 to 0ffffeb 16 0ffffe4 16 to 0ffffe7 16 0ffffe0 16 to 0ffffe3 16 0ffffdc 16 to 0ffffdf 16 4 bytes address
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 305 read check data this command reads the check data that confirms that the write data, which was sent with the page program command, was successfully received. (1) transfer the "fd 16 " command code with the 1st byte. (2) the check data (low) is received with the 2nd byte and the check data (high) with the 3rd. to use this read check data command, first execute the command and then initialize the check data. next, execute the page program command the required number of times. after that, when the read check command is executed again, the check data for all of the read data that was sent with the page program command during this time is read. the check data is the result of crc operation of write data. figure 1.32.37. timing for the read check data check data (low) rxd1 txd1 fd 16 (m16c reception data) (m16c transmit data) check data (high) baud rate 9600 this command changes baud rate to 9,600 bps. execute it as follows. (1) transfer the "b0 16 " command code with the 1st byte. (2) after the "b0 16 " check code is output with the 2nd byte, change the baud rate to 9,600 bps. figure 1.32.38. timing of baud rate 9600 rxd1 txd1 b0 16 (m16c reception data) (m16c transmit data) b0 16
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 306 baud rate 19200 this command changes baud rate to 19,200 bps. execute it as follows. (1) transfer the "b1 16 " command code with the 1st byte. (2) after the "b1 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. figure 1.32.39. timing of baud rate 19200 baud rate 38400 this command changes baud rate to 38,400 bps. execute it as follows. (1) transfer the "b2 16 " command code with the 1st byte. (2) after the "b2 16 " check code is output with the 2nd byte, change the baud rate to 38,400 bps. figure 1.32.40. timing of baud rate 38400 baud rate 57600 this command changes baud rate to 57,600 bps. execute it as follows. (1) transfer the "b3 16 " command code with the 1st byte. (2) after the "b3 16 " check code is output with the 2nd byte, change the baud rate to 57,600 bps. figure 1.32.41. timing of baud rate 57600 rxd1 txd1 b1 16 (m16c reception data) (m16c transmit data) b1 16 rxd1 txd1 b3 16 (m16c reception data) (m16c transmit data) b3 16 rxd1 txd1 b2 16 (m16c reception data) (m16c transmit data) b2 16
under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer appendix standard serial i/o mode 2 (flash memory version) 307 example circuit application for the standard serial i/o mode 2 the below figure shows a circuit application for the standard serial i/o mode 2. figure 1.32.43. example circuit application for the standard serial i/o mode 2 monitor output data input data output (1) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. rts1(busy) clk1 r x d1 t x d1 cnvss p5 0 (ce) p5 5 (epm) nmi m16c/80 flash memory version baud rate 115200 this command changes baud rate to 115,200 bps. execute it as follows. (1) transfer the "b4 16 " command code with the 1st byte. (2) after the "b4 16 " check code is output with the 2nd byte, change the baud rate to 19,200 bps. figure 1.32.42. timing of baud rate 115200 rxd1 txd1 b3 16 (m16c reception data) (m16c transmit data) b3 16
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 308 rev.a3 99.9.24 page 216 table 1.28.22 t h(bclk-dw) add page 222 figure 1.28.6 t h(bclk-cas) --> t h(bclk-dw) page 225 figure 1.28.9 wr, wrl, wrh(sepalate bus) wave change page 24 line 3 a software reset has almost the same ... --> a software reset has the same ... page 161 note 2: when f(x in ) is over 10 mhz, the f ad frequency must be under 10 mhz by dividing. - -> addition page 219 figure 1.28.3 tac2(ad-db)=(tcyc x n-35)ns.max (n= 1, 3 ... ) --> (n= 2, 3 ...) page 220 figure 1.28.4 tac3(rd-db)=(tcyc/2 x m-35)ns.max (m= 2 and 5 ...) --> (m= 3 and 5 ...) page 226 table 1.28.23 vt+vt- tb2 in --> tb5 in ta2 out --> ta0 in scl 2 -scl 4 , sda 2 - sda 3 --> addition page 227 table 1.28.25 note page 228 tables 1.28.26 and 1.28.27 pages 231-233 tables 1.28.39-1.28.41 page 241 figure 1.28.17 page 18 figure 1.4.3 (60) timer b3,4,5 count start flag value change page 19 figure 1.4.4 flash memory control register 0 and 1 added page 22 figure 1.5.3 flash memory control register 0 and 1 added page 43 figure 1.8.4 cm0 note 5 delate page 81 figure 1.11.5 dmai memory address reload register address dra2, dra3 000000 16 --> xxxxxx 16 page 181, 182 figures 1.25.4-1.25.5 d0-d15 waveform changed page 185 (6) pull up control register changed page 208 table 1.28.3 v t+ -v t- tb0 in -tb2 in --> tb0 in -tb5 in , ta2 out -ta4 out --> ta0 out -ta4 out page 213 table 1.28.19 page 214 table 1.28.20 page 215 table 1.28.21 page 216 table 1.28.22 page 218 figure 1.28.2 page 219 figure 1.28.3 page 220 figure 1.28.4 page 221 figure 1.28.5 page 222 figure 1.28.6 page 223 figure 1.28.7 page 225 figure 1.28.9 flash version addition page 2 figure 1.1.1 pin 1 p9 6 /anex1/txd 4 /sda 4 --> p9 6 /anex1/txd 4 /sda 4 / srxd 4 pin 5 p9 2 /tb2 in /txd 3 /sda 3 / stxd 3 --> p9 2 /tb2 in /txd 3 /sda 3 / srxd 3 rev.a1 99.5.14 revision history rev.a2 99.5.20 99.6.4 99.6.28 99.7.9
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 309 pin 6 p9 1 /tb1 in /rxd 3 /scl 3 --> p9 1 /tb1 in /rxd 3 /scl 3 / stxd 3 page 18 figure 1.4.3 pm1 reset value " c0h" --> " 00h" page 26 figure 1.6.2 is insralled pm1 reset value " c0h" --> " 00h" divided to mask and flash rom version. page 85 dma request bit line 9 addition "in this case, dmai request bit is cleared." page 85 internal factors the dmai request bit is cleared to "0" when the dma transfer starts. the dmai request bit can be cleared by the program. --> the dmai request bit is cleared to "0" when the dma transfer starts. even if dma transfer disable state (channel i transfer mode select bit is "00" and dmai transfer count register is "0"), the dmai request bit is cleared to "0". page 85 external factors when an external factor is selected, the dmai request bit is cleared, in the same way as the dmai request bit is cleared for internal factors, when the dma transfer starts. the dmai request bit can also be cleared by the program. --> when an external factor is selected, the dmai request bit is cleared, in the same way as the dmai request bit is cleared for internal factors, when the dma transfer starts or dma transfer disable state. page 210 timing requirement tac4 (cas-db) = - 35[ns] --> tac4 (cas-db) = - 35[ns] page 225 figure 1.28.9 memory expansion mode and microprocessor mode (valid only with wait) ______ ________ ________ ? wr, wrl, wrh (separate bus) timing rasing edge is wrong page 1 ? dmac...4 channels (trigger: 24 sources) --> 31 sources ? supply voltage 4.0 to 5.5v (f(xin)=20mhz) mask rom version 4.2 to 5.5v (f(xin)=20mhz) flash memory version 2.7 to 5.5v (f(xin)=10mhz) mask rom and flash memory version ? interrupt...4 software --> 5 software page 1,5 table 1.1.1 feature ? memory capacity rom 128 kbytes --> (see rom expansion figure.) ram 10k --> 10 to 24 kbytes interrupt...4 software --> 5 software page 2 figure 1.1.1 note addition, package: 144p6q --> 144p6q-a page 5 figure 1.1.4, table 1.1.2 m30805mg-xxxfp/gp addition page 6 figure1.1.5 rom capacity g:256 kbytes addition page 7 p00 to p07 however, it is possible to select pull-up resistance presence to the usable port as i/ o port by setting. --> addition cnvss connect it to the vss pin when operating in single-chip or memory expan- sion mode. connect it to the vcc pin when in microprocessor mode. --> connect it to the vss pin when operating in single-chip or memory expan- sion mode after reset. connect it to the vcc pin when in microprocessor mode after reset. byte when operating in single-chip mode,connect this pin to vss. --> when not using the external bus,connect this pin to vss. rev.b 14/3/'00 rev.a4 00.02.29 10 9 x n f(bclk) 10 9 x n f(bclk) x2
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 310 page 8 p50 to p57 in single chip mode, --> delate page 10 figure 1.2.1 m30805fg --> m30805mg/fg page 13 figure 1.4.3 (2) processor mode register c0 16 --> 00 16 page 20 to 23 figure 1.5.1 to 1.5.4 note addition page 25 figure 1.6.1, 1.6.2 figure 1.6.1 is divided to figure 1.6.1and 1.6.2 page 30 table 1.7.4 page 34 figure 1.7.3 note addition page 36 line 3 the chip select control register --> the wait control registe page 38, 39 figure 1.7.6, 1.7.7 note change page 42 line 7 addition when the main clock is stoped (bit 5 at address 0006 16 =1) or the mode is shifted to stop mode (bit 0 at address 0007 16 =1), the main clock division register (address 000c 16 ) is set to the divided-8 mode. page 42 (3)bclk when shifting to stop mode, --> when main clock is stoped or shifting to stop mode, page 43 figure 1.8.4 cm0 note 6 change, note 7, 8 addition, cm1 note 4 addition page 44 figure 1.8.5 note 2 change page 48 line 5 when shifting to stop mode and reset, --> when shifting to stop mode, reset or stopping main clock, (12) low power dissipation mode addition when the main clock is stoped, the main clock division register (address 000c 16 ) is set to the division by 8 mode. page 51 figure 1.8.7. clock transition note 3, 4 addition page 52 line 9 addition page 54 software interrupts (2) overflow interrupt, "cmpx" addition page 55 (2) peripheral i/o interrupts ? bus collision detection/start, stop condition (uart2, uart3, uart4) interrupts -- > change page 57 ? variable vector tables addition set an even address to the start address of vector table setting in intb so that operating efficiency is increased. page 58 table 1.9.3 software interrupt number 40, 41 fault errir --> addition page 71 address match interrupt line 7 addition _______ page 72 (3) the nmi interrupt _______ ? do not reset the cpu with the input to the nmi pin being in the l state. --> ? signal of "l" level width more than 1 clock of cpu operation clock (bclk) is _______ necessary for nmi pin. page 72 (4) external interrupt page 74 figure 1.10.1 page 76 line 2 "dmac is a function that to transmit 1 data of a source address (8 bits /16 bits) to a destination address when transmission request occurs. " addition. page 76 line 12 addition when writing to dsa2 and dsa3, set register bank select flag (b flag) to "1" and use ldc instruction to set sb and fb registers. page 76 figure 1.11.1 page 77 table 1.11.1 transfer memory space (16 mbyte space) --> addition
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 311 page 78 figure 1.11.2 note :6 or instruction --> or instruction etc. page 80 figure 1.11.4 drci ? transfer counter --> ? transfer count register page 81 figure 1.11.5 dmai, dsai, drai transfer count specification "(16 mbytes area)" addition drai memory address counter --> memory address register page 85 line 9 addition (1) internal factors, (2) external factors change page 87 fugure 1.12.1 "timer b2 overflow" addition page 88 fugure 1.12.2 timer a --> timer b2 overflow (to timer a count source) page 93 table 1.13.2 cout source ? tb2 overflows, taj overflows --> ?tb2 over- flows or underflows , taj overflows or underflows page 95 figure 1.13.7 when using two-phase signal processing note 3 --> addition page 102 figure 1.14.3 tbsr when reset 00 16 --> 000xxxxxx 16 b4-b0 when read, the value is "0" --> indeterminate page 104 table 1.14.2 cout source ? tbj overflows --> ?tbj overflows or underflows page 124 figure 1.16.5 uitb note 1 delate page 126-127 figure 1.16.7 to 1.16.8 crd change page 130 figure 1.16.11 sdhi enabled <--> disabled page 144 _______ _______ (a) separate cts/rts pins function (uart0) page 146 table 1.19.1 addition in "other things" page 147 figure 1.19.1 a "l" level returns from txd due to the occurrence of a parity error. --> a "l" level returns from sim card... page 149 figure 1.19.4 note addition page 150 table 1.20.1 note 1: lsb first --> msb first, note 3 change page 156 figure 1.20.4 4 to 5 cycles --> 3 to 6 cycles page 163, 165-169 figure 1.21.2-figure 1.21.8 adcon1 note 2-6 addition page 170 line 14,23 addition page 171 line 5 addition page 172 figure 1.22.3 note :3 d-a control register --> d-a register page 176 figure 1.24.3 page 178 figure 1.25.1 note 1 position change page 178 line 10 dram controler --> addition page 179 figure 1.25.2 note 1 --> change page 184 (1) direction registers, (2) port registers --> change page 185 (4) function select register b --> change page 189 figure 1.26.4 port pi direction register note 2 addition page 191 figure 1.26.6 port pi register note 1 and 2 addition page 193 table 1.26.1 note addition page 194 figure 1.26.8 function select register a1 note 1 addition page 196 figure 1.26.10 function select register b1 note 2 addition page 197 figure 1.26.11 function select register b3 note 1 --> addition, psl3_3-psl3_6 change page 198 figure 1.26.13 port control register note 2 addition page 199 figure 1.26.15 port pi direction register note 2 addition page 202 precaution on a-d converter (6) --> addition page 205 stop mode and wait mode (2) all clock stop bits --> all clock stop control bits page 205 noise addition page 205 precaution on interrupt (1) line 7 --> addition
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 312 page 206 making power consumption electricity small --> addition page 209 table 1.28.3 v t+ C v t- scl 2 -scl 4 , sda 2 -sda 4 addition page 210 table 1.28.5 note change page 217 table 1.28.22 t rp expression change page 221, 222, 224, 225, 227 figure 1.28.4, 1.28.5, 1.28.7, 1.28.8, 1.28.10 addition page 229 figure 1.28.12 refresh timing (self refresh) ras timing page 232 3v of electric characteristics addition page 248 table 1.29.1 data hold --> addition page 249 figure 1.29.2 package type 144p6q --> 144p6q-a page 250 flash memory line 5 change page 251 function outline line 24 (parallel ... function ) --> delate page 272 standard serial i/o mode line 26 externl device --> external device ( program- mer) page 288 figure1.31.21 programer --> peripheral unit ( programmer) page 43 figure1.8.4 note of the system clock control register 0-->addition page 44 line 4 note-->addition page 45 table1.8.2 note-->addition page 71 line 9 "address match interrupt is not generated with a start instruction of interrupt routine."-->delete page 73 (6) precaution of address mach interrupt-->addition page 79 figure1.11.2 note-->change page 87 precaution for dmac-->addition page 131 figure1.16.11 bit 7-->must set to "1" in selecting iic mode. page 152 figure1.20.1 bit 7-->must set to "1" in selecting iic mode. page 182 addition page 207 (3) address match interrupt in interrupt precautions-->addition page 208 (2) dmac-->addition page 209 precautions for using clk out pin-->addition page 212 table1.28.3 icc when clock stop topr=25c o -->change page 214 table1.28.6 external clock input high and low pulse waidth 22-->20 external clock rise and fall time 10-->5 page 217, 218 table1.28.19, 20 t h(bclk-db) -->delete, t w(wr) -->addition page 220 table1.28.22 t h(bclk-db) -5ns --> -7ns page 235 table1.28.23 icc when clock stop topr=25c o -->change page 237 table1.28.27 t h(cas-db) -->addition page 240, 241 table1.28.39, 40 t w(wr) -->addition, t h(bclk-rd) 0ns-->-3ns page 242 table1.28.41 t d(ad-ale) =10 9 /(f (bclk) x2)-20 -->10 9 /(f (bclk) x2)-27 page 243 table1.28.42 t h(bclk-cas) 0ns-->-3ns page 244 figure1.28.15 t ac1(rd-db) min-->max, t ac1(ad-db) min-->max page 245 figure1.28.16 t ac2(rd-db) min-->max, t ac2(ad-db) min-->max page 246, 255 figure1.28.17 2 wait, figure1.28.18 3 wait-->addition page 248 figure1.28.19 t ac3(ad-db) -->addition, t su(db-rd) -->t su(db-bclk) , t h(bclk-rd) 0ns -- >-3ns, t d(ad-ale) =(tcyc/2-20)ns--> ... -27)ns page 249 figure1.28.20 addition page 250, 251 figure1.28.21, 1.28.22 -->addition page 252 figure1.28.23 t h(bclk-db) -->t h(cas-db) rev.b3 17/6/'00
contents for change revision date version under development preliminary specifications rev.b specifications in this manual are tentative and subject to change. mitsubishi microcomputers m16c/80 (144-pin version) group single-chip 16-bit cmos microcomputer revision history 313 page 253 figure 1.28.24 t d(db-cas) -->t su(db-cas) , t h(bclk-cas)--> t h(bclk-db) page 254 figure1.28.25 t d(cas-ras) -->t su(cas-ras) page 257 table1.29.1 power supply (under planning)-->delete, program/erase voltage f(x in )-->f( bclk ), 2.7v-5.5v-->delete
keep safety first in your circuit designs! notes regarding these materials l mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. l these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. l mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. l all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). l when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. l mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. l the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. l if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/or the country of destination is prohibited. l please contact mitsubishi electric corporation or an authorized mitsubishi semicon ductor product distributor for further details on these materials or the products con tained therein.
mitsubishi semiconductors m16c/80 (144-pin version) group data sheet rev.b3 june first edition 2000 editioned by committee of editing of mitsubishi semiconductor data sheet published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?2000 mitsubishi electric corporation

▲Up To Search▲

Price & Availability of M30802MC-XXXGP

	To Download M30802MC-XXXGP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .